公开(公告)号：US20240211138A1

公开(公告)日：2024-06-27

申请号：US18145339

申请日：2022-12-22

Applicant: Xilinx, Inc.

Inventor： Aman Gupta ,  Krishnan Srinivasan ,  Shishir Kumar ,  Sagheer Ahmad ,  Ahmad R. Ansari

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0629 ,  G06F3/0673

Abstract: A system includes a plurality of processing elements and a plurality of memory controllers. The system includes a network on chip (NoC) providing connectivity between the plurality of processing elements and the plurality of memory controllers. The NoC includes a sparse network coupled to the plurality of processing elements and a non-blocking network coupled to the sparse network and the plurality of memory controllers. The plurality of processing elements execute a plurality of applications. Each application has a same deterministic memory access performance in accessing associated ones of the plurality of memory controllers via the sparse network and the non-blocking network of the NoC.

公开(公告)号：US12019908B2

公开(公告)日：2024-06-25

申请号：US17389272

申请日：2021-07-29

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Shishir Kumar ,  Sagheer Ahmad ,  Abbas Morshed ,  Aman Gupta

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0653 ,  G06F3/0679

Abstract: Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.