公开(公告)号：US20230370392A1

公开(公告)日：2023-11-16

申请号：US17663376

申请日：2022-05-13

Applicant: Xilinx, Inc.

Inventor： Krishnan Srinivasan ,  Sagheer Ahmad ,  Ygal Arbel ,  Aman Gupta

IPC: H04L49/109

CPC classification number: H04L49/109

Abstract: An integrated circuit (IC) includes a Network-on-Chip (NoC). The NoC includes a plurality of NoC master circuits, a plurality of NoC slave circuits, and a plurality of switches. The plurality of switches are interconnected and communicatively link the plurality of NoC master circuits with the plurality of NoC slave circuits. The plurality of switches are configured to receive data of different widths during operation and implement different operating modes for forwarding the data based on the different widths.

公开(公告)号：US11832035B2

公开(公告)日：2023-11-28

申请号：US17232207

申请日：2021-04-16

Applicant: XILINX, INC.

Inventor： Aman Gupta ,  Sagheer Ahmad ,  Ygal Arbel ,  Abbas Morshed ,  Eun Mi Kim

IPC: H04Q3/00 ,  G06F13/16 ,  G06F13/40

CPC classification number: H04Q3/0004 ,  G06F13/1668 ,  G06F13/4027

Abstract: Embodiments herein describe an integrated circuit that includes a NoC with at least two levels of switching: a sparse network and a non-blocking network. In one embodiment, the non-blocking network is a localized interconnect that provides an interface between the sparse network in the NoC and a memory system that requires additional bandwidth such as HBM2/3 or DDR5. Hardware elements connected to the NoC that do not need the additional benefits provided by the non-blocking network can connect solely to the sparse network. In this manner, the NoC provides a sparse network (which has a lower density of switching elements) for providing communication between lower bandwidth hardware elements and a localized non-blocking network for facilitating communication between the sparse network and higher bandwidth hardware elements.

公开(公告)号：US20240211138A1

公开(公告)日：2024-06-27

申请号：US18145339

申请日：2022-12-22

Applicant: Xilinx, Inc.

Inventor： Aman Gupta ,  Krishnan Srinivasan ,  Shishir Kumar ,  Sagheer Ahmad ,  Ahmad R. Ansari

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0629 ,  G06F3/0673

Abstract: A system includes a plurality of processing elements and a plurality of memory controllers. The system includes a network on chip (NoC) providing connectivity between the plurality of processing elements and the plurality of memory controllers. The NoC includes a sparse network coupled to the plurality of processing elements and a non-blocking network coupled to the sparse network and the plurality of memory controllers. The plurality of processing elements execute a plurality of applications. Each application has a same deterministic memory access performance in accessing associated ones of the plurality of memory controllers via the sparse network and the non-blocking network of the NoC.

公开(公告)号：US11985061B1

公开(公告)日：2024-05-14

申请号：US17227258

申请日：2021-04-09

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Abbas Morshed ,  Aman Gupta ,  Sagheer Ahmad

IPC: H04L45/302 ,  G06F15/78 ,  H04L45/00 ,  H04L45/42 ,  H04L45/745

CPC classification number: H04L45/302 ,  G06F15/7825 ,  H04L45/42 ,  H04L45/566 ,  H04L45/745 ,  H04L45/34

Abstract: Embodiments herein describe an integrated circuit that includes a network on chip (NoC) where an egress logic block or switch performs a route lookup for a subsequent (e.g., downstream) switch in the NoC (referred to herein as look-ahead routing). After receiving the packet and a port ID from the egress logic block or the switch, the downstream switch knows, without performing route lookup of its own, on which port it should forward the packet. Thus, if the downstream switch performs other functions that are dependent on knowing the destination port (e.g., arbitration or QoS updating), the downstream switch can perform those functions immediately since the port ID was already determined by, and received from, the previous network element.

公开(公告)号：US12093394B2

公开(公告)日：2024-09-17

申请号：US18111808

申请日：2023-02-20

Applicant: XILINX, INC.

Inventor： Aman Gupta ,  James D. Wesselkamper ,  James Anderson ,  Nader Sharifi ,  Ahmad R. Ansari ,  Sagheer Ahmad ,  Brian C. Gaide

IPC: G06F21/57 ,  H04L9/06 ,  H04L9/08 ,  H04L9/14 ,  H04L9/30

CPC classification number: G06F21/575 ,  H04L9/0618 ,  H04L9/0822 ,  H04L9/0861 ,  H04L9/14 ,  H04L9/30 ,  G06F2221/034

Abstract: Some examples described herein provide for securely booting a heterogeneous integration circuitry apparatus. In an example, an apparatus (e.g., heterogeneous integration circuitry) includes a first portion and a second portion of one or more entropy sources on a first component and a second component, respectively. The apparatus also includes a key generation circuit communicatively coupled with the first portion and the second portion to generate a key encrypted key based on a first set of bits output by the first portion and a second set of bits output by the second portion. The apparatus also includes a key security circuit to generate, based on the key encrypted key and an encrypted public key stored at the apparatus, a plaintext public key to be used by a boot loader during a secure booting operation for the apparatus.

公开(公告)号：US12047275B2

公开(公告)日：2024-07-23

申请号：US17705087

申请日：2022-03-25

Applicant: XILINX, INC.

Inventor： Aman Gupta ,  Jaideep Dastidar ,  Jeffrey Cuppett ,  Sagheer Ahmad

IPC: H04L45/24 ,  H04L45/74 ,  H04L49/109

CPC classification number: H04L45/24 ,  H04L45/74 ,  H04L49/109

Abstract: Methods and apparatus relating to transmission on physical channels, such as in networks on chips (NoCs) or between chiplets, are provided. One example apparatus generally includes a higher bandwidth client; a lower bandwidth client; a first destination; a second destination; and multiple physical channels coupled between the higher bandwidth client, the lower bandwidth client, the first destination, and the second destination, wherein the higher bandwidth client is configured to send first traffic, aggregated across the multiple physical channels, to the first destination and wherein the lower bandwidth client is configured to send second traffic, concurrently with sending the first traffic, from the lower bandwidth client, dispersed over two or more of the multiple physical channels, to the second destination.

公开(公告)号：US12244518B2

公开(公告)日：2025-03-04

申请号：US17663376

申请日：2022-05-13

Applicant: Xilinx, Inc.

Inventor： Krishnan Srinivasan ,  Sagheer Ahmad ,  Ygal Arbel ,  Aman Gupta

IPC: H04L49/109

Abstract: An integrated circuit (IC) includes a Network-on-Chip (NoC). The NoC includes a plurality of NoC master circuits, a plurality of NoC slave circuits, and a plurality of switches. The plurality of switches are interconnected and communicatively link the plurality of NoC master circuits with the plurality of NoC slave circuits. The plurality of switches are configured to receive data of different widths during operation and implement different operating modes for forwarding the data based on the different widths.

公开(公告)号：US12235782B2

公开(公告)日：2025-02-25

申请号：US18086531

申请日：2022-12-21

Applicant: XILINX, INC.

Inventor： Aman Gupta ,  Krishnan Srinivasan ,  Ahmad R. Ansari ,  Sagheer Ahmad

IPC: G06F13/40 ,  G06F12/1009

Abstract: Embodiments herein describe a multi-chip device that includes multiple ICs with interconnected NoCs. Embodiments herein provided address translation circuitry in the ICs. The address translation circuitry establish a hierarchy where traffic originating for a first IC that is intended for a destination on a second IC is first routed to the address translation circuitry on the second IC which then performs an address translation and inserts the traffic back on the NoC in the second IC but with a destination ID corresponding to the destination. In this manner, the IC can have additional address apertures only to route traffic to the address translation circuitry of the other ICs rather than having address apertures for every destination in the other ICs.

公开(公告)号：US12019908B2

公开(公告)日：2024-06-25

申请号：US17389272

申请日：2021-07-29

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Shishir Kumar ,  Sagheer Ahmad ,  Abbas Morshed ,  Aman Gupta

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0653 ,  G06F3/0679

Abstract: Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.

公开(公告)号：US11983264B2

公开(公告)日：2024-05-14

申请号：US17457839

申请日：2021-12-06

Applicant: XILINX, INC.

Inventor： Jaideep Dastidar ,  Aman Gupta ,  Krishnan Srinivasan ,  Sagheer Ahmad

IPC: G06F21/54 ,  G06F21/62 ,  G06F21/85

CPC classification number: G06F21/54 ,  G06F21/6209 ,  G06F21/85

Abstract: Embodiments herein describe offloading encryption activities to a network interface controller/card (NIC) (e.g., a SmartNIC) which frees up server compute resources to focus on executing customer applications. In one embodiment, the smart NIC includes a system on a chip (SoC) implemented on an integrated circuit (IC) that includes an embedded processor. Instead of executing a transport layer security (TLS) stack entirely in the embedded processor, the embodiments herein offload certain TLS tasks to a Public Key Infrastructure (PKI) accelerator such as generating public-private key pairs.