公开(公告)号：US12235782B2

公开(公告)日：2025-02-25

申请号：US18086531

申请日：2022-12-21

Applicant: XILINX, INC.

Inventor： Aman Gupta ,  Krishnan Srinivasan ,  Ahmad R. Ansari ,  Sagheer Ahmad

IPC: G06F13/40 ,  G06F12/1009

Abstract: Embodiments herein describe a multi-chip device that includes multiple ICs with interconnected NoCs. Embodiments herein provided address translation circuitry in the ICs. The address translation circuitry establish a hierarchy where traffic originating for a first IC that is intended for a destination on a second IC is first routed to the address translation circuitry on the second IC which then performs an address translation and inserts the traffic back on the NoC in the second IC but with a destination ID corresponding to the destination. In this manner, the IC can have additional address apertures only to route traffic to the address translation circuitry of the other ICs rather than having address apertures for every destination in the other ICs.

公开(公告)号：US12019908B2

公开(公告)日：2024-06-25

申请号：US17389272

申请日：2021-07-29

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Shishir Kumar ,  Sagheer Ahmad ,  Abbas Morshed ,  Aman Gupta

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0653 ,  G06F3/0679

Abstract: Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.

公开(公告)号：US11983264B2

公开(公告)日：2024-05-14

申请号：US17457839

申请日：2021-12-06

Applicant: XILINX, INC.

Inventor： Jaideep Dastidar ,  Aman Gupta ,  Krishnan Srinivasan ,  Sagheer Ahmad

IPC: G06F21/54 ,  G06F21/62 ,  G06F21/85

CPC classification number: G06F21/54 ,  G06F21/6209 ,  G06F21/85

Abstract: Embodiments herein describe offloading encryption activities to a network interface controller/card (NIC) (e.g., a SmartNIC) which frees up server compute resources to focus on executing customer applications. In one embodiment, the smart NIC includes a system on a chip (SoC) implemented on an integrated circuit (IC) that includes an embedded processor. Instead of executing a transport layer security (TLS) stack entirely in the embedded processor, the embodiments herein offload certain TLS tasks to a Public Key Infrastructure (PKI) accelerator such as generating public-private key pairs.

公开(公告)号：US11784149B1

公开(公告)日：2023-10-10

申请号：US17235843

申请日：2021-04-20

Applicant: XILINX, INC.

Inventor： Ygal Arbel ,  Kenneth Ma ,  Balakrishna Jayadev ,  Sagheer Ahmad

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L24/16 ,  H01L23/5384 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/0651 ,  H01L2924/1434

Abstract: Embodiments herein describe a multiple die system that includes an interposer that connects a first die to a second die. Each die has a bump interface structure that is connected to the other structure using traces in the interposer. However, the bump interface structures may have different orientations relative to each other, or one of the interface structures defines fewer signals than the other. Directly connecting the corresponding signals defined by the structures to each other may be impossible to do in the interposer, or make the interposer too costly. Instead, the embodiments here simplify routing in the interposer by connecting the signals in the bump interface structures in a way that simplifies the routing but jumbles the signals. The jumbled signals can then be corrected using reordering circuitry in the dies (e.g., in the link layer and physical layer).

公开(公告)号：US11709624B2

公开(公告)日：2023-07-25

申请号：US15898183

申请日：2018-02-15

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Ian A. Swarbrick ,  Sagheer Ahmad

IPC: G06F3/06 ,  G06F13/40 ,  G06F1/28 ,  G06F1/3287

CPC classification number: G06F3/0659 ,  G06F1/28 ,  G06F1/3287 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0679 ,  G06F13/4022 ,  G06F2213/0038

Abstract: Examples of the present disclosure generally relate to integrated circuits, such as a system-on-chip (SoC), that include a memory subsystem. In some examples, an integrated circuit includes a first master circuit in a first power domain on a chip; a second master circuit in a second power domain on the chip; and a first memory controller in a third power domain on the chip. The first master circuit and the second master circuit each are configured to access memory via the first memory controller. The first power domain and the second power domain each are separate and independent from the third power domain.

公开(公告)号：US20200327089A1

公开(公告)日：2020-10-15

申请号：US16380860

申请日：2019-04-10

Applicant: Xilinx, Inc.

Inventor： Jaideep Dastidar ,  Sagheer Ahmad ,  Ian A. Swarbrick

IPC: G06F13/42 ,  G06F13/28 ,  G06F13/40

Abstract: Examples herein describe a peripheral I/O device with a hybrid gateway that permits the device to have both I/O and coherent domains. That is, the I/O device can benefit from a traditional I/O model where the I/O device driver manages some of the compute resources in the I/O device as well as the benefits of adding other compute resources in the I/O device to the same coherent domain used by the hardware in the host computing system. As result, the compute resources in the coherent domain of the peripheral I/O device can communicate with the host in a similar manner as, e.g., CPU-to-CPU communication in the host. At the same time, the compute resources in the I/O domain can benefit from the advantages of the traditional I/O device model which provides efficiencies when doing large memory transfers between the host and the I/O device (e.g., DMA).

公开(公告)号：US10698842B1

公开(公告)日：2020-06-30

申请号：US16380856

申请日：2019-04-10

Applicant: Xilinx, Inc.

Inventor： Jaideep Dastidar ,  Sagheer Ahmad

IPC: G06F13/12 ,  G06F9/38 ,  G06F9/50 ,  G06F9/54 ,  G06F12/0815

Abstract: Examples herein describe a peripheral I/O device with a domain assist processor (DAP) and a domain specific accelerator (DSA) that are in the same coherent domain as CPUs and memory in a host computing system. Peripheral I/O devices were previously unable to participate in a cache-coherent shared-memory multiprocessor paradigm with hardware resources in the host computing system. As a result, domain assist processing for lightweight processor functions (e.g., open source functions such as gzip, open source crypto libraries, open source network switches, etc.) either are performed using CPUs resources in the host or by provisioning a special processing system in the peripheral I/O device (e.g., using programmable logic in a FPGA). The embodiments herein use a DAP in the peripheral I/O device to perform the lightweight processor functions that would otherwise be performed by hardware resources in the host or by a special processing system in the peripheral I/O device.

公开(公告)号：US20190391929A1

公开(公告)日：2019-12-26

申请号：US16016349

申请日：2018-06-22

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Sagheer Ahmad ,  Gaurav Singh

IPC: G06F12/1027 ,  H03K19/177

Abstract: An example programmable integrated circuit (IC) includes a processing system having a processor, a master circuit, and a system memory management unit (SMMU). The SMMU includes a first translation buffer unit (TBU) coupled to the master circuit, an address translation (AT) circuit, an AT interface coupled to the AT circuit, and a second TBU coupled to the AT circuit, and programmable logic coupled to the AT circuit in the SMMU through the AT interface.

公开(公告)号：US20190250853A1

公开(公告)日：2019-08-15

申请号：US15898183

申请日：2018-02-15

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Ian A. Swarbrick ,  Sagheer Ahmad

IPC: G06F3/06 ,  G06F13/40 ,  G06F1/28

CPC classification number: G06F3/0659 ,  G06F1/28 ,  G06F1/3287 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0679 ,  G06F13/4022 ,  G06F2213/0038

Abstract: Examples of the present disclosure generally relate to integrated circuits, such as a system-on-chip (SoC), that include a memory subsystem. In some examples, an integrated circuit includes a first master circuit in a first power domain on a chip; a second master circuit in a second power domain on the chip; and a first memory controller in a third power domain on the chip. The first master circuit and the second master circuit each are configured to access memory via the first memory controller. The first power domain and the second power domain each are separate and independent from the third power domain.

公开(公告)号：US09378102B1

公开(公告)日：2016-06-28

申请号：US14452858

申请日：2014-08-06

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Bradley L. Taylor ,  Giulio Corradi

IPC: G06F11/07 ,  G06F11/20 ,  H03K19/177 ,  H03K19/007

CPC classification number: G06F11/2007 ,  H03K19/007 ,  H03K19/17764

Abstract: A system on a chip (SoC) for providing safety hardware fault tolerance and/or safety software fault tolerance includes a first safety sub-system having a first safety channel; a second safety sub-system having a second safety channel; and a third sub-system. The first safety sub-system is independent of the second safety sub-system to allow the second safety sub-system to communicate through the second safety channel when the first safety sub-system or the third subsystem fails, and further to allow the first safety sub-system to communicate through the first safety channel when the second safety sub-system or the third subsystem fails.

Abstract translation: 用于提供安全硬件容错和/或安全软件容错的芯片系统（SoC）包括具有第一安全通道的第一安全子系统; 具有第二安全通道的第二安全子系统; 和第三个子系统。 第一安全子系统独立于第二安全子系统，以允许第二安全子系统在第一安全子系统或第三子系统失效时通过第二安全通道进行通信，并且还允许第一安全子系统 子系统在第二安全子系统或第三子系统出现故障时通过第一安全通道进行通信。