公开(公告)号：US11386020B1

公开(公告)日：2022-07-12

申请号：US16808054

申请日：2020-03-03

Applicant: XILINX, INC.

Inventor： Matthew H. Klein ,  Goran Hk Bilski ,  Juan Jose Noguera Serra ,  Ismed D. Hartanto ,  Sridhar Subramanian ,  Tim Tuan

IPC: G06F15/17 ,  G06F13/16 ,  G06F9/30 ,  H03K19/1776 ,  G06F7/501 ,  G06F15/173

Abstract: Some examples described herein relate to programmable devices that include a data processing engine (DPE) array that permits shifting of where an application is loaded onto DPEs of the DPE array. In an example, a programmable device includes a DPE array. The DPE array includes DPEs and address index offset logic. Each of the DPEs includes a processor core and a memory mapped switch. The processor core is programmable via one or more memory mapped packets routed through the respective memory mapped switch. The memory mapped switches in the DPE array are coupled together to form a memory mapped interconnect network. The address index offset logic is configurable to selectively modify which DPE in the DPE array is targeted by a respective memory mapped packet routed in the memory mapped interconnect network.

公开(公告)号：US20220100691A1

公开(公告)日：2022-03-31

申请号：US17035368

申请日：2020-09-28

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Tim Tuan ,  Sridhar Subramanian

IPC: G06F13/40 ,  G06F13/16

Abstract: A multi-die integrated circuit (IC) can include an interposer and a first die coupled to the interposer. The first die can include a data processing engine (DPE) array, wherein the DPE array includes a plurality of DPEs and a DPE interface coupled to the plurality of DPEs. The DPE interface has a logical interface and a physical interface. The multi-die IC also can include a second die coupled to the interposer. The second die can include a die interface. The DPE interface and the die interface are configured to communicate through the interposer.

公开(公告)号：US20230289311A1

公开(公告)日：2023-09-14

申请号：US18320147

申请日：2023-05-18

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Tim Tuan ,  Sridhar Subramanian

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4027 ,  G06F13/1668

Abstract: An integrated circuit includes an interposer and a die coupled to the interposer. The die includes a first data processing engine (DPE) array and a second DPE array. The first DPE array includes a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs. The second DPE array includes a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs. The integrated circuit includes one or more other dies having a first die interface coupled to, and configured to communicate with, the first DPE interface via the interposer and a second die interface coupled to, and configured to communicate with, the second DPE interface via the interposer.

公开(公告)号：US11693808B2

公开(公告)日：2023-07-04

申请号：US17654543

申请日：2022-03-11

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Tim Tuan ,  Sridhar Subramanian

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4027 ,  G06F13/1668

Abstract: An integrated circuit includes an interposer, a first die coupled to the interposer, a second die coupled to the interposer, and a third die coupled to the interposer and having a plurality of die interfaces. The first die includes a first data processing engine (DPE) array having a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs therein. The second die includes a second DPE array having a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs therein. The first DPE interface of the first die is configured to communicate with a first die interface of the plurality of die interfaces via the interposer. The second DPE interface of the second die is configured to communicate with a second die interface of the plurality of die interfaces via the interposer.

公开(公告)号：US20220197846A1

公开(公告)日：2022-06-23

申请号：US17654543

申请日：2022-03-11

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Tim Tuan ,  Sridhar Subramanian

IPC: G06F13/40 ,  G06F13/16

Abstract: An integrated circuit includes an interposer, a first die coupled to the interposer, a second die coupled to the interposer, and a third die coupled to the interposer and having a plurality of die interfaces. The first die includes a first data processing engine (DPE) array having a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs therein. The second die includes a second DPE array having a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs therein. The first DPE interface of the first die is configured to communicate with a first die interface of the plurality of die interfaces via the interposer. The second DPE interface of the second die is configured to communicate with a second die interface of the plurality of die interfaces via the interposer.

公开(公告)号：US11288222B1

公开(公告)日：2022-03-29

申请号：US17035368

申请日：2020-09-28

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Tim Tuan ,  Sridhar Subramanian

IPC: G06F13/40 ,  G06F13/16

Abstract: A multi-die integrated circuit (IC) can include an interposer and a first die coupled to the interposer. The first die can include a data processing engine (DPE) array, wherein the DPE array includes a plurality of DPEs and a DPE interface coupled to the plurality of DPEs. The DPE interface has a logical interface and a physical interface. The multi-die IC also can include a second die coupled to the interposer. The second die can include a die interface. The DPE interface and the die interface are configured to communicate through the interposer.

公开(公告)号：US12001367B2

公开(公告)日：2024-06-04

申请号：US18320147

申请日：2023-05-18

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Tim Tuan ,  Sridhar Subramanian

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4027 ,  G06F13/1668

Abstract: An integrated circuit includes an interposer and a die coupled to the interposer. The die includes a first data processing engine (DPE) array and a second DPE array. The first DPE array includes a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs. The second DPE array includes a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs. The integrated circuit includes one or more other dies having a first die interface coupled to, and configured to communicate with, the first DPE interface via the interposer and a second die interface coupled to, and configured to communicate with, the second DPE interface via the interposer.