公开(公告)号：US20240184552A1

公开(公告)日：2024-06-06

申请号：US18073219

申请日：2022-12-01

Applicant: XILINX, INC.

Inventor： Steven Leslie POPE ,  Dmitri KITARIEV ,  Neil Duncan TURTON ,  Ripduman Singh SOHAN ,  Stephan DIESTELHORST

IPC: G06F8/41

CPC classification number: G06F8/4434 ,  G06F8/447

Abstract: A method comprises compiling, by a compiler, a received program to provide a compiler output for configuring hardware to implement the received program. The received program relate to packets of data in a memory. The compiling comprising defining by the compiler output a plurality of computational units in the hardware, each of the computational units being configured to receive a packet of data as a stream of words and between a first and a second of the computational units, a first buffer for storing words of a packet and a second buffer for storing data output by the first computational unit.

公开(公告)号：US20230224261A1

公开(公告)日：2023-07-13

申请号：US17571292

申请日：2022-01-07

Applicant: XILINX, INC.

Inventor： Steven Leslie POPE ,  Derek Edward ROBERTS ,  Dmitri KITARIEV ,  Neil Duncan TURTON ,  David James RIDDOCH ,  Ripduman SOHAN ,  Stephan DIESTELHORST

IPC: H04L49/00 ,  H04L49/25 ,  H04L49/20 ,  H04L49/90 ,  G06F13/28

CPC classification number: H04L49/30 ,  H04L49/25 ,  H04L49/20 ,  H04L49/90 ,  G06F13/28

Abstract: A network interface device has data path circuitry configured to cause data to be moved into and/or out of the network interface device. The data path circuitry comprises: first circuitry for providing one or more data processing operations; and interface circuitry supporting channels. The channels comprises command channels receiving command information from a plurality of data path circuitry user instances, event channels providing respective command completion information to the plurality of data path user instances; and data channels providing the associated data.

公开(公告)号：US20240193117A1

公开(公告)日：2024-06-13

申请号：US18080604

申请日：2022-12-13

Applicant: XILINX, INC.

Inventor： Nachiket Ganesh KAPRE ,  Kimon KARRAS ,  Dmitri KITARIEV ,  Neil Duncan TURTON ,  (none) SIDDHARTHA ,  Stephan DIESTELHORST ,  Thilini Kaushalya Bandara DASSANAYAKE MUDIYANSELAGE

IPC: G06F13/40 ,  G06F7/57

CPC classification number: G06F13/4045 ,  G06F7/57 ,  G06F13/4022

Abstract: Embodiments herein describe a configurable packet processing architecture for a SmartNIC or other network device. The configurable architecture includes a plurality of PPEs which are communicatively coupled using a packet bus. A packet can be processed in each of the PPEs. For example, each packet may be first processed by PPE 1, then PPE 2, then PPE 3, and so forth. Moreover, the results of processing the packet at a PPE 1 may affect the operation performed on the packet when it reaches PPE 2 or PPE 3. Thus, the PPEs form a chain where the results determined by a first PPE when processing the packet can affect or change the operation a second PPE performs when processing the same packet.