公开(公告)号：US07913144B2

公开(公告)日：2011-03-22

申请号：US12513401

申请日：2007-10-24

申请人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

发明人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

IPC分类号： G06F11/00

CPC分类号： G01R31/31705 ,  G01R31/318307 ,  G01R31/318342 ,  G01R31/318392

摘要： Provided are a diagnostic device and the like providing a favorable diagnosis result by further improving the diagnosis resolution. A diagnostic device 1 has a symbol injection part 3, which is composed of a symbol injection part for an active element 5 and a symbol injection part for a passive element 7, an occurrence probability providing part 9, an equal occurrence probability providing part 11, and a switching part 13. A per-test X-fault diagnosis flow by the diagnostic device 1 consists of a stage for collecting diagnostic information and a stage for drawing diagnostic conclusion. The layout of a deep-submicron LSI circuit usually needs to involve multiple layers, which means that vias are extensively used. Since via information is utilized by the symbol injection part for a passive element 7, it becomes possible to locate defects to the via level, greatly improving the diagnostic resolution. Since, by the occurrence probability providing part 9, a new diagnosis value is used and, the occurrence probabilities of possible faulty logic combinations are taken into consideration, the reality in a deep-submicron LSI circuit is better reflected, which contributes to the improvement of diagnostic resolution.

摘要翻译： 通过进一步提高诊断分辨率，提供诊断装置等提供有利的诊断结果。 诊断装置1具有符号注入部3，其由有源元件5的符号注入部和无源元7的符号注入部，发生概率提供部9，等发生概率提供部11， 以及切换部13.诊断装置1的每个测试X故障诊断流程包括用于收集诊断信息的阶段和用于绘制诊断结论的阶段。 深亚微米LSI电路的布局通常需要涉及多层，这意味着通孔被广泛使用。 由于无源元件7的符号注入部使用通孔信息，因此可以将缺陷定位到通孔电平，大大提高诊断分辨率。 由于通过发生概率提供部9使用新的诊断值，并且考虑了可能的故障逻辑组合的发生概率，所以更好地反映了深亚微米LSI电路中的现实，这有助于改善 诊断分辨率。

公开(公告)号：US20100205491A1

公开(公告)日：2010-08-12

申请号：US12761654

申请日：2010-04-16

申请人： Kohei Miyase ,  Xiaoqing Wen ,  Seiji Kajihara

发明人： Kohei Miyase ,  Xiaoqing Wen ,  Seiji Kajihara

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： H03K19/23 ,  G01R31/318371

摘要： The provided are logic value determination method and program for identifying unspecified bits and determining their logic values shortly. The method enables to control the total number of logic value differences between corresponding input and output lines of combinational circuit. The method includes the first step for determining, when output has a logic value and input has an unspecified value, that the unspecified bit has the logic value of output, the second step for determining, when output has an unspecified value and input has a logic value, the logic value of the unspecified bit by justification, and the third step for calculating, when input and output both have unspecified values, probabilities of output to have 0 and 1, and determining the logic value of the unspecified bit based on the difference between the probabilities. The third step is repeated until the total number reaches a target value.

摘要翻译： 提供的是用于识别未指定位并且很快确定其逻辑值的逻辑值确定方法和程序。 该方法能够控制组合电路的相应输入和输出线之间的逻辑值差的总数。 该方法包括用于当输出具有逻辑值且输入具有未指定值时确定未指定位具有输出逻辑值的第一步骤，用于当输出具有未指定值并且输入具有逻辑时确定的第二步骤 值，未指定位的逻辑值，以及当输入和输出都具有未指定值时计算的第三步骤，输出的概率为0和1，以及基于差异来确定未指定位的逻辑值 概率之间。 重复第三步，直到总数达到目标值。

公开(公告)号：US20090019327A1

公开(公告)日：2009-01-15

申请号：US12235628

申请日：2008-09-23

申请人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

发明人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318544 ,  G01R31/318502

摘要： A generation apparatus and the like for generating a test vector set capable of reducing differences in a logic value generated before and after a scan capture for outputs from scan cells included in a full-scan sequential circuit are provided. A generation apparatus 200 generating an initial test vector set 216 for a logic circuit includes a target vector identification unit 204 identifying a test vector satisfying a predetermined criterion and to be selected for the number of bits (the number of bit transitions) whose logic values differ before and after scan capture with respect to outputs from scan cells included in the sequential circuit, from among test vectors in the initial test vector set 216, and a test vector set conversion unit 206 converting the test vector identified by the test vector identification unit 204 and to be selected so as to reduce the number of bit transitions with respect to outputs from the scan cells included in the sequential circuit.

摘要翻译： 提供了一种用于生成能够减少在扫描捕获之前和之后产生的逻辑值中的差异的测试向量集的生成装置等，用于从全扫描时序电路中包括的扫描单元的输出。 生成用于逻辑电路的初始测试向量集合216的生成装置200包括：目标矢量识别单元204，其识别满足预定标准的测试向量，并且对于其逻辑值不同的位数（位数转换的数量）来选择 相对于包括在顺序电路中的扫描单元的输出，从初始测试向量集合216的测试向量中的扫描捕获之前和之后，以及转换由测试向量识别单元204识别的测试向量的测试向量集合转换单元206 并且被选择为减少相对于包括在顺序电路中的扫描单元的输出的位转换的数量。

公开(公告)号：US20100095179A1

公开(公告)日：2010-04-15

申请号：US12597106

申请日：2009-04-11

申请人： Xiaoqing Wen ,  Kohei Miyase ,  Seiji Kajihara

发明人： Xiaoqing Wen ,  Kohei Miyase ,  Seiji Kajihara

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318307 ,  G01R31/31813 ,  G01R31/318371

摘要： A test pattern generation method for determining if a combinational portion 17 is defective, by applying test patterns to a semiconductor integrated circuit 10 and comparing responses to the test patterns with expected responses, the method including: a first step of generating test patterns having logic bits for detecting defects and unspecified bits; a second step of selecting critical paths 19, 19a, 19b generated by the application of the test patterns; a third step of identifying critical gates on the critical paths 19, 19a, 19b; and a fourth step of determining unspecified bits so that a critical capture transition metric, which indicates the number of the critical gates whose states are changed, is reduced; wherein by reducing the critical capture transition metric, output delays from the critical paths 19, 19a, 19b are prevented, and thereby false testing can be avoided.

摘要翻译： 一种测试图形生成方法，用于通过将测试图案应用于半导体集成电路10并且将测试图案的响应与期望的响应进行比较来确定组合部分17是否有缺陷，该方法包括：产生具有逻辑位的测试图案的第一步骤 用于检测缺陷和未指定位; 选择通过应用测试图形生成的关键路径19,19a，19b的第二步骤; 在关键路径19,19a，19b上识别关键闸门的第三步骤; 以及确定未指定位的第四步骤，使得指示其状态改变的关键门的数量的关键捕获转换度量被减小; 其中通过减小关键捕获转移度量，防止从关键路径19,19a，19b的输出延迟，从而可以避免错误测试。

公开(公告)号：US07979765B2

公开(公告)日：2011-07-12

申请号：US12442996

申请日：2007-09-25

申请人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

发明人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G11C29/10 ,  G01R31/31721 ,  G01R31/31813 ,  G01R31/31917 ,  G11C29/56004

摘要： Provided are a generation device and the like for generating a test vector which can reduce capture power efficiently. The generation device 100 generates a test vector for a logic circuit by assigning logic values to each of a plurality of unspecified bits (X-bits) included in a test cube. The generation device 100 includes a selection unit 101 for selecting, among the plurality of X-bits, a target X-bit, which is a target of assigning a logic value, a capture transition metric calculation unit 103 for calculating capture transition metric caused by a test cube including an X-bit, and a logic value assignment unit 105 for assigning, to the selected target X-bit, a logic value which causes the smaller capture transition metric, by applying the capture transition metric calculation means to a first test cube obtained by assigning a logic value 0 to the selected target X-bit and to a second test cube obtained by assigning a logic value 1 to the selected target X-bit, and by comparing a capture transition metric caused by a first test cube and a capture transition metric caused by a second test cube.

摘要翻译： 提供了用于生成能够有效地降低捕获功率的测试向量的生成装置等。 生成装置100通过向包括在测试立方体中的多个未指定位（X位）中的每一个分配逻辑值来生成用于逻辑电路的测试向量。 生成装置100包括：选择单元101，用于在多个X位中选择作为分配逻辑值的目标的目标X位;捕获转移度量计算单元103，用于计算由 包括X位的测试立方体和用于通过将捕获转移度量计算装置应用于第一测试来向所选择的目标X位分配导致较小捕获转换度量的逻辑值的逻辑值分配单元105 通过将逻辑值0分配给所选择的目标X位获得的立方体以及通过将逻辑值1分配给所选择的目标X位获得的第二测试立方体，并且通过将由第一测试立方体引起的捕获转变度量与 由第二个测试立方体引起的捕获转换度量。

公开(公告)号：US07962822B2

公开(公告)日：2011-06-14

申请号：US12235628

申请日：2008-09-23

申请人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

发明人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

IPC分类号： G01R31/28

CPC分类号： G01R31/318544 ,  G01R31/318502

摘要： A generation apparatus and the like for generating a test vector set capable of reducing differences in a logic value generated before and after a scan capture for outputs from scan cells included in a full-scan sequential circuit are provided. A generation apparatus 200 generating an initial test vector set 216 for a logic circuit includes a target vector identification unit 204 identifying a test vector satisfying a predetermined criterion and to be selected for the number of bits (the number of bit transitions) whose logic values differ before and after scan capture with respect to outputs from scan cells included in the sequential circuit, from among test vectors in the initial test vector set 216, and a test vector set conversion unit 206 converting the test vector identified by the test vector identification unit 204 and to be selected so as to reduce the number of bit transitions with respect to outputs from the scan cells included in the sequential circuit.

摘要翻译： 提供了一种用于生成能够减少在扫描捕获之前和之后产生的逻辑值中的差异的测试向量集的生成装置等，用于从全扫描时序电路中包括的扫描单元的输出。 生成用于逻辑电路的初始测试向量集合216的生成装置200包括：目标矢量识别单元204，其识别满足预定标准的测试向量，并且对于其逻辑值不同的位数（位数转换的数量）来选择 相对于包括在顺序电路中的扫描单元的输出，从初始测试向量集合216的测试向量中的扫描捕获之前和之后，以及转换由测试向量识别单元204识别的测试向量的测试向量集合转换单元206 并且被选择为减少相对于包括在顺序电路中的扫描单元的输出的位转换的数量。

公开(公告)号：US20090319842A1

公开(公告)日：2009-12-24

申请号：US12442996

申请日：2007-09-25

申请人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

发明人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

IPC分类号： G06F11/25 ,  G01R31/28

CPC分类号： G11C29/10 ,  G01R31/31721 ,  G01R31/31813 ,  G01R31/31917 ,  G11C29/56004

摘要： Provided are a generation device and the like for generating a test vector which can reduce capture power efficiently. The generation device 100 generates a test vector for a logic circuit by assigning logic values to each of a plurality of unspecified bits (X-bits) included in a test cube. The generation device 100 includes a selection unit 101 for selecting, among the plurality of X-bits, a target X-bit, which is a target of assigning a logic value, a capture transition metric calculation unit 103 for calculating capture transition metric caused by a test cube including an X-bit, and a logic value assignment unit 105 for assigning, to the selected target X-bit, a logic value which causes the smaller capture transition metric, by applying the capture transition metric calculation means to a first test cube obtained by assigning a logic value 0 to the selected target X-bit and to a second test cube obtained by assigning a logic value 1 to the selected target X-bit, and by comparing a capture transition metric caused by a first test cube and a capture transition metric caused by a second test cube.

摘要翻译： 提供了用于生成能够有效地降低捕获功率的测试向量的生成装置等。 生成装置100通过向包括在测试立方体中的多个未指定位（X位）中的每一个分配逻辑值来生成用于逻辑电路的测试向量。 生成装置100包括：选择单元101，用于在多个X位中选择作为分配逻辑值的目标的目标X位;捕获转移度量计算单元103，用于计算由 包括X位的测试立方体和用于通过将捕获转移度量计算装置应用于第一测试来向所选择的目标X位分配导致较小捕获转换度量的逻辑值的逻辑值分配单元105 通过将逻辑值0分配给所选择的目标X位获得的立方体以及通过将逻辑值1分配给所选择的目标X位获得的第二测试立方体，并且通过将由第一测试立方体引起的捕获转变度量与 由第二个测试立方体引起的捕获转换度量。

公开(公告)号：US08453023B2

公开(公告)日：2013-05-28

申请号：US12761654

申请日：2010-04-16

申请人： Kohei Miyase ,  Xiaoqing Wen ,  Seiji Kajihara

发明人： Kohei Miyase ,  Xiaoqing Wen ,  Seiji Kajihara

IPC分类号： G01R31/28

CPC分类号： H03K19/23 ,  G01R31/318371

摘要： Logic value determination method and program for identifying unspecified bits and determining logic values shortly. The method enables to control the total number of logic value differences between corresponding input and output lines of combinational circuit. The method includes the first step for determining, when output has a logic value and input has an unspecified value, that the unspecified bit has the logic value of output, the second step for determining, when output has an unspecified value and input has a logic value, the logic value of the unspecified bit by justification, and the third step for calculating, when input and output both have unspecified values, probabilities of output to have 0 and 1, and determining the logic value of the unspecified bit based on the difference between the probabilities. The third step is repeated until the total number reaches a target value.

摘要翻译： 用于识别未指定位的逻辑值确定方法和程序，并且不久将确定逻辑值。 该方法能够控制组合电路的相应输入和输出线之间的逻辑值差的总数。 该方法包括用于当输出具有逻辑值且输入具有未指定值时确定未指定位具有输出逻辑值的第一步骤，用于当输出具有未指定值并且输入具有逻辑时确定的第二步骤 值，未指定位的逻辑值，以及当输入和输出都具有未指定值时计算的第三步骤，输出的概率为0和1，以及基于差异来确定未指定位的逻辑值 概率之间。 重复第三步，直到总数达到目标值。

公开(公告)号：US08001437B2

公开(公告)日：2011-08-16

申请号：US12597106

申请日：2008-04-11

申请人： Xiaoqing Wen ,  Kohei Miyase ,  Seiji Kajihara

发明人： Xiaoqing Wen ,  Kohei Miyase ,  Seiji Kajihara

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/318307 ,  G01R31/31813 ,  G01R31/318371

摘要： A test pattern generation method for determining if a combinational portion 17 is defective, by applying test patterns to a semiconductor integrated circuit 10 and comparing responses to the test patterns with expected responses, the method including: a first step of generating test patterns having logic bits for detecting defects and unspecified bits; a second step of selecting critical paths 19, 19a, 19b generated by the application of the test patterns; a third step of identifying critical gates on the critical paths 19, 19a, 19b; and a fourth step of determining unspecified bits so that a critical capture transition metric, which indicates the number of the critical gates whose states are changed, is reduced; wherein by reducing the critical capture transition metric, output delays from the critical paths 19, 19a, 19b are prevented, and thereby false testing can be avoided.

摘要翻译： 一种测试图形生成方法，用于通过将测试图案应用于半导体集成电路10并且将测试图案的响应与期望的响应进行比较来确定组合部分17是否有缺陷，该方法包括：产生具有逻辑位的测试图案的第一步骤 用于检测缺陷和未指定位; 选择通过应用测试图形生成的关键路径19,19a，19b的第二步骤; 在关键路径19,19a，19b上识别关键闸门的第三步骤; 以及确定未指定位的第四步骤，使得指示其状态改变的关键门的数量的关键捕获转换度量被减小; 其中通过减小关键捕获转移度量，防止从关键路径19,19a，19b的输出延迟，从而可以避免错误测试。

公开(公告)号：US20100064191A1

公开(公告)日：2010-03-11

申请号：US12513401

申请日：2007-10-24

申请人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

发明人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/31705 ,  G01R31/318307 ,  G01R31/318342 ,  G01R31/318392

摘要： Provided are a diagnostic device and the like providing a favorable diagnosis result by further improving the diagnosis resolution. A diagnostic device 1 has a symbol injection part 3, which is composed of a symbol injection part for an active element 5 and a symbol injection part for a passive element 7, an occurrence probability providing part 9, an equal occurrence probability providing part 11, and a switching part 13. A per-test X-fault diagnosis flow by the diagnostic device 1 consists of a stage for collecting diagnostic information and a stage for drawing diagnostic conclusion. The layout of a deep-submicron LSI circuit usually needs to involve multiple layers, which means that vias are extensively used. Since via information is utilized by the symbol injection part for a passive element 7, it becomes possible to locate defects to the via level, greatly improving the diagnostic resolution. Since, by the occurrence probability providing part 9, a new diagnosis value is used and, the occurrence probabilities of possible faulty logic combinations are taken into consideration, the reality in a deep-submicron LSI circuit is better reflected, which contributes to the improvement of diagnostic resolution.

摘要翻译： 通过进一步提高诊断分辨率，提供诊断装置等提供有利的诊断结果。 诊断装置1具有符号注入部3，其由有源元件5的符号注入部和无源元7的符号注入部，发生概率提供部9，等发生概率提供部11， 以及切换部13.诊断装置1的每个测试X故障诊断流程包括用于收集诊断信息的阶段和用于绘制诊断结论的阶段。 深亚微米LSI电路的布局通常需要涉及多层，这意味着通孔被广泛使用。 由于无源元件7的符号注入部使用通孔信息，因此可以将缺陷定位到通孔电平，大大提高诊断分辨率。 由于通过发生概率提供部9使用新的诊断值，并且考虑了可能的故障逻辑组合的发生概率，所以更好地反映了深亚微米LSI电路中的现实，这有助于改善 诊断分辨率。