公开(公告)号：US10789402B1

公开(公告)日：2020-09-29

申请号：US16400690

申请日：2019-05-01

Applicant: Xilinx, Inc.

Inventor： Kumar S. S. Vemuri ,  Abid Karumannil ,  Venkataraju Koppada ,  Anitha Barri ,  Anusha Perla ,  Vishal K. Jain ,  Sairam K. M. Menon ,  Anil K. Martha

IPC: G06F30/327 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: Examples herein describe a method for a compiler and hardware-abstraction-layer architecture for a programmable integrated circuit (IC). In one embodiment, a method for mapping and porting a neural network to an integrated circuit (IC) is disclosed. The method includes receiving a network description of the neural network; generating a framework independent network graph based on the network description; performing a plurality of back-end operations on the network graph to generate an execution sequence vector; and configuring the IC based on the execution sequence vector.

公开(公告)号：US20250086007A1

公开(公告)日：2025-03-13

申请号：US18464829

申请日：2023-09-11

Applicant: Xilinx, Inc.

Inventor： Sumit Nagpal ,  Abid Karumannil

IPC: G06F9/48 ,  G06F9/50

Abstract: Scheduling kernels on a system with heterogeneous compute circuits includes receiving, by a hardware processor, a plurality of kernels and a graph including a plurality of nodes corresponding to the plurality of kernels. The graph defines a control flow and a data flow for the plurality of kernels. The kernels are implemented within different ones of a plurality of compute circuits coupled to the hardware processor. A set of buffers for performing a job for the graph are allocated based, at least in part, on the data flow specified by the graph. Different ones of the kernels as implemented in the compute circuits are invoked based on the control flow defined by the graph.

公开(公告)号：US11561826B1

公开(公告)日：2023-01-24

申请号：US17096136

申请日：2020-11-12

Applicant: Xilinx, Inc.

Inventor： Sumit Nagpal ,  Abid Karumannil ,  Vishal Jain ,  Arun Kumar Patil

IPC: G06F9/46 ,  G06F9/48 ,  G06F16/901 ,  G06N3/08

Abstract: Scheduling work of a machine learning application includes instantiating kernel objects by a computer processor in response to input of kernel definitions. Each kernel object is of a kernel type indicating a compute circuit. The computer processor generates a graph in a memory. Each node represents a task and specifies an assignment of the task to one or more of the kernel objects, and each edge represents a data dependency. Task queues are created in the memory and assigned to queue tasks represented by the nodes. Kernel objects are assigned to the task queues, and the tasks are enqueued by threads executing the kernel objects, based on assignments of the kernel objects to the task queues and assignments of the tasks to the kernel objects. Tasks are dequeued by the threads, and the compute circuits are activated to initiate processing of the dequeued tasks.