公开(公告)号：US11036546B1

公开(公告)日：2021-06-15

申请号：US16385880

申请日：2019-04-16

Applicant: Xilinx, Inc.

Inventor： Kumud Bhandari ,  Ajit K. Agarwal

IPC: G06F9/48 ,  G06F9/54 ,  G06F16/901 ,  G06F8/10 ,  G06F15/78 ,  G06F30/20 ,  G06F11/34

Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges. A compiler converts the source code into a bit stream and/or object code which configures a heterogeneous processing environment of a SoC to execute the graph. Before implementing the dataflow graph on the SoC, the programmer may wish to simulate the dataflow graph. In one embodiment, each kernel in the dataflow graph is assigned a respective thread. Additionally, the simulator can include a runtime library for simulating the different types of communication links between the kernels. Even those these communication links are different protocols or have different semantics, using the simulation components in the library makes the different types of communication links composable so they can inter-operate in the same simulation environment.

公开(公告)号：US12182552B2

公开(公告)日：2024-12-31

申请号：US17664858

申请日：2022-05-24

Applicant: Xilinx, Inc.

Inventor： Ajit K. Agarwal

IPC: G06F8/41

Abstract: A computer-based technique for processing an application includes determining that a loop of the application includes a reference to a data item of a vector data type. A trip count of the loop is determined to have an unknown trip count. The loop is split into a first loop and a second loop based on a splitting factor. The second loop is unrolled.

公开(公告)号：US20240176942A1

公开(公告)日：2024-05-30

申请号：US18057199

申请日：2022-11-18

Applicant: Xilinx, Inc.

Inventor： Ajit K. Agarwal

IPC: G06F30/398 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392

Abstract: Providing dataflow based guidance for buffer allocation in a multicore circuit architecture includes converting, using computer hardware, an application specified in a high-level programming language into an intermediate representation. Buffers of dataflows of the intermediate representation are detected. Determining whether the buffers are independent or dependent based on an analysis of the dataflows of the intermediate representation. Buffer constraints are generated. The buffer constraints specify whether the buffers are independent and dictate a mapping of the buffers in the multicore circuit architecture.

公开(公告)号：US10860766B1

公开(公告)日：2020-12-08

申请号：US16420881

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Mukund Sivaraman ,  Shail Aditya Gupta ,  Akella Sastry ,  Rishi Surendran ,  Philip B. James-Roxby ,  Samuel R. Bayliss ,  Vinod K. Kathail ,  Ajit K. Agarwal ,  Ralph D. Wittig

IPC: G06F30/347 ,  G06F8/41 ,  G06F16/901 ,  G06F30/394 ,  G06F12/1081 ,  G06F115/02

Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

公开(公告)号：US20230385040A1

公开(公告)日：2023-11-30

申请号：US17664858

申请日：2022-05-24

Applicant: Xilinx, Inc.

Inventor： Ajit K. Agarwal

IPC: G06F8/41

CPC classification number: G06F8/443

Abstract: A computer-based technique for processing an application includes determining that a loop of the application includes a reference to a data item of a vector data type. A trip count of the loop is determined to have an unknown trip count. The loop is split into a first loop and a second loop based on a splitting factor. The second loop is unrolled.

公开(公告)号：US20200372200A1

公开(公告)日：2020-11-26

申请号：US16420881

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Mukund Sivaraman ,  Shail Aditya Gupta ,  Akella Sastry ,  Rishi Surendran ,  Philip B. James-Roxby ,  Samuel R. Bayliss ,  Vinod K. Kathail ,  Ajit K. Agarwal ,  Ralph D. Wittig

IPC: G06F30/347 ,  G06F8/41 ,  G06F16/901 ,  G06F12/1081 ,  G06F30/394

Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.