公开(公告)号：US11144687B1

公开(公告)日：2021-10-12

申请号：US16370260

申请日：2019-03-29

Applicant: Xilinx, Inc.

Inventor： Pramod Chandraiah ,  Roger Ng ,  Alain Darte ,  Radharamanan Radhakrishnan ,  Peter Frey ,  Kumar Deepak

IPC: G06F30/30

Abstract: Disclosed approaches monitor states of a plurality of sets of a plurality of handshake signals. Each set of handshake signals is associated with a respective one sub-circuit of a plurality of sub-circuits. For each sub-circuit, a beginning of an iteration by the sub-circuit is detected based on states of the plurality of handshake signals of the set associated with the sub-circuit. A graphics object is generated in response to detecting the beginning of the iteration. The graphics object is displayed on a display device and overlaid on a timeline associated with the sub-circuit. The graphics object has a bound that corresponds to the beginning of the iteration. The end of the iteration is detected based on the states of the associated set of handshake signals, and the graphics object is bounded on the timeline to indicate the end of the iteration.

公开(公告)号：US11314911B1

公开(公告)日：2022-04-26

申请号：US17331835

申请日：2021-05-27

Applicant: Xilinx, Inc.

Inventor： Fangqing Du ,  Sheng Wang ,  Alain Darte ,  Alexandre Isoard ,  Hem C. Neema ,  Lin-Ya Yu

IPC: G06F30/327 ,  G06F30/337

Abstract: High-level synthesis implementation of data structures in hardware can include detecting, within a design and using computer hardware, a data structure and a compiler directive for the data structure. The design may be specified in a high-level programming language. Using the computer hardware and based on the compiler directive, a modified version of the design may be created by, at least in part, generating a modified version of the data structure based on the compiler directive. Using the computer hardware, a circuit design may be generated from the modified version of the design by creating, at least in part, a hardware memory architecture for the circuit design and mapping the modified version of the data structure onto the hardware memory architecture.