公开(公告)号：US11238199B1

公开(公告)日：2022-02-01

申请号：US17116720

申请日：2020-12-09

Applicant: Xilinx, Inc.

Inventor： Alexandre Isoard ,  Lin-Ya Yu ,  Hem C. Neema

IPC: G06F30/30 ,  G06F30/327 ,  G06F30/323 ,  G06F16/22 ,  G06F111/20

Abstract: A computer-based high-level synthesis (HLS) technique for circuit implementation includes providing a library as a data structure, wherein the library includes a function configured to perform a vector operation using one or more vector(s). The library can include a software construct defining a variable number of elements included in the vector(s). The number of elements can be determined from a variable included in an HLS application that uses the library to perform the function. The variable can specify an arbitrary positive integer value. The method also can include generating a circuit design from the HLS application. The circuit design can implement the function in hardware to perform the vector operation in one clock cycle. A data type of each element of the vector(s) may be specified as a further software construct within the library and determined from a further variable of the HLS application.

公开(公告)号：US20240176936A1

公开(公告)日：2024-05-30

申请号：US18059348

申请日：2022-11-28

Applicant: Xilinx, Inc.

Inventor： Lin-Ya Yu ,  Alexandre Isoard ,  Hem C. Neema

IPC: G06F30/327

CPC classification number: G06F30/327

Abstract: Implementing burst transfers for predicated accesses in high-level synthesis includes generating, using computer hardware, an intermediate representation of a design specified in a high-level programming language. The design is for an integrated circuit. Using the computer hardware, loop predicate information for one or more conditional statements within a loop body of the intermediate representation is determined. A plurality of memory accesses of the loop body guarded by the one or more conditional statements are determined to be sequential memory accesses based on the predicate information. The intermediate representation is modified by inserting one or more intrinsics therein indicating that the sequential memory accesses are to be implemented using a burst transfer mode of the integrated circuit.

公开(公告)号：US11314911B1

公开(公告)日：2022-04-26

申请号：US17331835

申请日：2021-05-27

Applicant: Xilinx, Inc.

Inventor： Fangqing Du ,  Sheng Wang ,  Alain Darte ,  Alexandre Isoard ,  Hem C. Neema ,  Lin-Ya Yu

IPC: G06F30/327 ,  G06F30/337

Abstract: High-level synthesis implementation of data structures in hardware can include detecting, within a design and using computer hardware, a data structure and a compiler directive for the data structure. The design may be specified in a high-level programming language. Using the computer hardware and based on the compiler directive, a modified version of the design may be created by, at least in part, generating a modified version of the data structure based on the compiler directive. Using the computer hardware, a circuit design may be generated from the modified version of the design by creating, at least in part, a hardware memory architecture for the circuit design and mapping the modified version of the data structure onto the hardware memory architecture.

公开(公告)号：US20240411967A1

公开(公告)日：2024-12-12

申请号：US18333372

申请日：2023-06-12

Applicant: Xilinx, Inc.

Inventor： Lin-Ya Yu ,  Alexandre Isoard ,  Hem C. Neema

IPC: G06F30/323

Abstract: High-level synthesis of designs using loop-aware execution information includes generating, using computer hardware, an intermediate representation (IR) of a design specified in a high-level programming language. The design is for an integrated circuit. Execution information analysis is performed on the IR of the design generating analysis results for functions of the design. The analysis results of the design are transformed by embedding the analysis results in a plurality of regions of the IR of the design. Selected regions of the plurality of regions are merged based on the analysis results, as embedded, for the selected regions. The IR of the design is scheduled using the analysis results subsequent to the merging.

公开(公告)号：US11836426B1

公开(公告)日：2023-12-05

申请号：US17819884

申请日：2022-08-15

Applicant: Xilinx, Inc.

Inventor： Fangqing Du ,  Alexandre Isoard ,  Lin-Ya Yu ,  Hem C. Neema

IPC: G06F30/327 ,  G06F15/80

CPC classification number: G06F30/327 ,  G06F15/80

Abstract: Detecting sequential access violations for high-level synthesis (HLS) includes performing a simulation, using computer hardware, of an application for HLS. During the simulation, accesses of the application to elements of an array of the application are detected. During the simulation, determinations of whether the accesses occur in a sequential order are made. An indication of whether the access occur in sequential order is generated.

公开(公告)号：US20230305949A1

公开(公告)日：2023-09-28

申请号：US17656236

申请日：2022-03-24

Applicant: Xilinx, Inc.

Inventor： Lin-Ya Yu ,  Alexandre Isoard ,  Hem C. Neema

IPC: G06F11/36 ,  G06F8/30

CPC classification number: G06F11/3688 ,  G06F8/311

Abstract: Static and automatic realization of inter-basic block burst transfers for high-level synthesis can include generating an intermediate representation of a design specified in a high-level programming language, wherein the intermediate representation is specified as a control flow graph, and detecting a plurality of basic blocks in the control flow graph. A determination can be made that plurality of basic blocks represent a plurality of consecutive memory accesses. A sequential access object specifying the plurality of consecutive memory accesses of the plurality of basic blocks is generated. A hardware description language (HDL) version of the design is generated, wherein the plurality of consecutive memory accesses are designated in the HDL version for implementation in hardware using a burst mode.

公开(公告)号：US11762762B1

公开(公告)日：2023-09-19

申请号：US17656236

申请日：2022-03-24

Applicant: Xilinx, Inc.

Inventor： Lin-Ya Yu ,  Alexandre Isoard ,  Hem C. Neema

IPC: G06F11/36 ,  G06F8/30

CPC classification number: G06F11/3688 ,  G06F8/311

Abstract: Static and automatic realization of inter-basic block burst transfers for high-level synthesis can include generating an intermediate representation of a design specified in a high-level programming language, wherein the intermediate representation is specified as a control flow graph, and detecting a plurality of basic blocks in the control flow graph. A determination can be made that plurality of basic blocks represent a plurality of consecutive memory accesses. A sequential access object specifying the plurality of consecutive memory accesses of the plurality of basic blocks is generated. A hardware description language (HDL) version of the design is generated, wherein the plurality of consecutive memory accesses are designated in the HDL version for implementation in hardware using a burst mode.