公开(公告)号：US11836426B1

公开(公告)日：2023-12-05

申请号：US17819884

申请日：2022-08-15

Applicant: Xilinx, Inc.

Inventor： Fangqing Du ,  Alexandre Isoard ,  Lin-Ya Yu ,  Hem C. Neema

IPC: G06F30/327 ,  G06F15/80

CPC classification number: G06F30/327 ,  G06F15/80

Abstract: Detecting sequential access violations for high-level synthesis (HLS) includes performing a simulation, using computer hardware, of an application for HLS. During the simulation, accesses of the application to elements of an array of the application are detected. During the simulation, determinations of whether the accesses occur in a sequential order are made. An indication of whether the access occur in sequential order is generated.

公开(公告)号：US11314911B1

公开(公告)日：2022-04-26

申请号：US17331835

申请日：2021-05-27

Applicant: Xilinx, Inc.

Inventor： Fangqing Du ,  Sheng Wang ,  Alain Darte ,  Alexandre Isoard ,  Hem C. Neema ,  Lin-Ya Yu

IPC: G06F30/327 ,  G06F30/337

Abstract: High-level synthesis implementation of data structures in hardware can include detecting, within a design and using computer hardware, a data structure and a compiler directive for the data structure. The design may be specified in a high-level programming language. Using the computer hardware and based on the compiler directive, a modified version of the design may be created by, at least in part, generating a modified version of the data structure based on the compiler directive. Using the computer hardware, a circuit design may be generated from the modified version of the design by creating, at least in part, a hardware memory architecture for the circuit design and mapping the modified version of the data structure onto the hardware memory architecture.