公开(公告)号：US11196715B2

公开(公告)日：2021-12-07

申请号：US16513218

申请日：2019-07-16

Applicant: XILINX, INC.

Inventor： Anujan Varma ,  Poching Sun ,  Chuan Cheng Pan ,  Suchithra Ravi

IPC: H04L29/06 ,  G06F1/3287 ,  G06F21/60 ,  G06F21/64

Abstract: A system comprises one or more slice-aggregated cryptographic slices each configured to perform a plurality of operations on an incoming data transfer at a first processing rate by aggregating one or more individual cryptographic slices each configured to perform the plurality of operations on a portion of the incoming data transfer at a second processing rate. Each of the individual cryptographic slices comprises in a serial connection an ingress block configured to take the portion of the incoming data transfer at the second processing rate, a cryptographic engine configured to perform the operations on the portion of the incoming data transfer, an egress block configured to process a signature of the portion and output the portion of the incoming data transfer once the operations have completed. The first processing rate of each slice-aggregated cryptographic slices equals aggregated second processing rates of the individual cryptographic slices in the slice-aggregated cryptographic slice.

公开(公告)号：US10659437B1

公开(公告)日：2020-05-19

申请号：US16144705

申请日：2018-09-27

Applicant: Xilinx, Inc.

Inventor： Ravi Sunkavalli ,  Anujan Varma ,  Chuan Cheng Pan ,  Patrick C. McCarthy ,  Hanh Hoang

IPC: H04L29/06

Abstract: A circuit arrangement includes an encryption circuit and a decryption circuit. A cryptographic shell circuit has a transmit channel and a receive channel in parallel with the transmit channel. The transmit channel includes an encryption interface circuit coupled to the encryption circuit. The encryption interface circuit determines first cryptographic parameters based on data in a plaintext input packet and inputs the first cryptographic parameters and plaintext input packet to the encryption circuit. The receive channel includes a decryption interface circuit coupled to the decryption circuit. The decryption interface circuit determines second cryptographic parameters based on data in a ciphertext input packet and inputs the second cryptographic parameters and ciphertext input packet to the decryption circuit. The encryption circuit encrypts the plaintext input packet based on the first cryptographic parameters, and the decryption circuit decrypts the ciphertext input packet based on the second cryptographic parameters.