公开(公告)号：US09341668B1

公开(公告)日：2016-05-17

申请号：US14242760

申请日：2014-04-01

Applicant: Xilinx, Inc.

Inventor： Ganesh Hariharan ,  Raghunandan Chaware ,  Glenn O'Rourke ,  Inderjit Singh ,  Eric J. Thorne ,  David E. Schweigler

IPC: G01R31/00 ,  G01R31/26 ,  G01R1/04

CPC classification number: G01R31/2889 ,  G01R1/0416

Abstract: A testable circuit arrangement includes an integrated circuit (IC) package. The IC package includes a package substrate, an interposer mounted directly on the package substrate with level 1 interconnects, and at least one IC die mounted directly on the interposer with level 0 interconnects. The package substrate of the IC package is mounted directly on a connector board with a soldered ball grid array of level 2 interconnects. The level 0, level 1, and level 2 interconnects include respective power, configuration, and test interconnects. Power, configuration, and test terminals of the connector board are coupled to the power, configuration, and test interconnects of the level 2 interconnects.

Abstract translation: 可测试电路装置包括集成电路（IC）封装。 IC封装包括封装衬底，直接安装在具有级别1互连的封装衬底上的插入件以及直接安装在具有0级互连的插入器上的至少一个IC管芯。 IC封装的封装基板直接安装在具有2级互连的焊接球栅格阵列的连接器板上。 0级，1级和2级互连包括各自的功率，配置和测试互连。 连接器板的电源，配置和测试端子耦合到2级互连的电源，配置和测试互连。