公开(公告)号：US11848670B2

公开(公告)日：2023-12-19

申请号：US17659423

申请日：2022-04-15

申请人： Xilinx, Inc.

发明人： Juan J. Noguera Serra ,  Tim Tuan ,  Javier Cabezas Rodriguez ,  David Clarke ,  Peter McColgan ,  Zachary Blaise Dickman ,  Saurabh Mathur ,  Amarnath Kasibhatla ,  Francisco Barat Quesada

IPC分类号： H03K19/1776 ,  G11C5/02 ,  H03K19/17764 ,  H03K19/17784

CPC分类号： H03K19/1776 ,  G11C5/025 ,  H03K19/17764 ,  H03K19/17784

摘要： An apparatus includes a data processing array having a plurality of array tiles. Each array tile can include a random-access memory (RAM) having a local memory interface accessible by circuitry within the array tile and an adjacent memory interface accessible by circuitry disposed within an adjacent array tile. Each adjacent memory interface of each array tile can include isolation logic that is programmable to allow the circuitry disposed within the adjacent array tile to access the RAM or prevent the circuitry disposed within the adjacent array tile from accessing the RAM. The data processing array can be subdivided into a plurality of partitions wherein the isolation logic of the adjacent memory interfaces is programmed to prevent array tiles from accessing RAMs across a boundary between the plurality of partitions.

公开(公告)号：US20240088900A1

公开(公告)日：2024-03-14

申请号：US18509128

申请日：2023-11-14

申请人： Xilinx, Inc.

发明人： Juan J. Noguera Serra ,  Tim Tuan ,  Javier Cabezas Rodriguez ,  David Clarke ,  Peter McColgan ,  Zachary Blaise Dickman ,  Saurabh Mathur ,  Amarnath Kasibhatla ,  Francisco Barat Quesada

IPC分类号： H03K19/1776 ,  G11C5/02 ,  H03K19/17764 ,  H03K19/17784

CPC分类号： H03K19/1776 ,  G11C5/025 ,  H03K19/17764 ,  H03K19/17784

摘要： An apparatus includes a data processing array having a plurality of array tiles. The plurality of array tiles include a plurality of compute tiles. The compute tiles include a core coupled to a random-access memory (RAM) in a same compute tile and to a RAM of at least one other compute tile. The data processing array is subdivided into a plurality of partitions. Each partition includes a plurality of array tiles including at least one of the plurality of compute tiles. The apparatus includes a plurality of clock gate circuits being programmable to selectively gate a clock signal provided to a respective one of the plurality of partitions.

公开(公告)号：US20230336179A1

公开(公告)日：2023-10-19

申请号：US17659423

申请日：2022-04-15

申请人： Xilinx, Inc.

发明人： Juan J. Noguera Serra ,  Tim Tuan ,  Javier Cabezas Rodriguez ,  David Clarke ,  Peter McColgan ,  Zachary Blaise Dickman ,  Saurabh Mathur ,  Amarnath Kasibhatla ,  Francisco Barat Quesada

IPC分类号： H03K19/1776 ,  H03K19/17784 ,  H03K19/17764 ,  G11C5/02

CPC分类号： H03K19/1776 ,  H03K19/17784 ,  H03K19/17764 ,  G11C5/025

摘要： An apparatus includes a data processing array having a plurality of array tiles. Each array tile can include a random-access memory (RAM) having a local memory interface accessible by circuitry within the array tile and an adjacent memory interface accessible by circuitry disposed within an adjacent array tile. Each adjacent memory interface of each array tile can include isolation logic that is programmable to allow the circuitry disposed within the adjacent array tile to access the RAM or prevent the circuitry disposed within the adjacent array tile from accessing the RAM. The data processing array can be subdivided into a plurality of partitions wherein the isolation logic of the adjacent memory interfaces is programmed to prevent array tiles from accessing RAMs across a boundary between the plurality of partitions.