公开(公告)号：US11223351B1

公开(公告)日：2022-01-11

申请号：US17163189

申请日：2021-01-29

Applicant: XILINX, INC.

Inventor： Amarnath Kasibhatla ,  Saurabh Mathur ,  Mansi Shrikant Patwardhan ,  Tim Tuan

IPC: H03K17/28 ,  G06F1/04 ,  H03K17/00

Abstract: A switch with clock-gating control and a method for clock gating a switch are described herein. In one example, the method generally includes detecting a state of one or more input ports and a state of one or more output ports of the switch, determining whether the state of the one or more input ports and the state of the one or more output ports has been stable for a preset number of clock cycles, and gating the switch from a clock signal until the state of the one or more input ports or the state of the one or more output ports change upon determining the states have been stable for the preset number of the cycles.

公开(公告)号：US12164451B2

公开(公告)日：2024-12-10

申请号：US17663824

申请日：2022-05-17

Applicant: Xilinx, Inc.

Inventor： David Patrick Clarke ,  Peter McColgan ,  Juan J. Noguera Serra ,  Tim Tuan ,  Saurabh Mathur ,  Amarnath Kasibhatla ,  Javier Cabezas Rodriguez ,  Pedro Miguel Parola Duarte ,  Zachary Blaise Dickman

IPC: G06F13/28 ,  G06F15/80

Abstract: An integrated circuit (IC) can include a data processing array including a plurality of compute tiles arranged in a grid. The IC can include an array interface coupled to the data processing array. The array interface includes a plurality of interface tiles. Each interface tile includes a plurality of direct memory access circuits. The IC can include a network-on-chip (NoC) coupled to the array interface. Each direct memory access circuit is communicatively linked to the NoC via an independent communication channel.

公开(公告)号：US11848670B2

公开(公告)日：2023-12-19

申请号：US17659423

申请日：2022-04-15

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Tim Tuan ,  Javier Cabezas Rodriguez ,  David Clarke ,  Peter McColgan ,  Zachary Blaise Dickman ,  Saurabh Mathur ,  Amarnath Kasibhatla ,  Francisco Barat Quesada

IPC: H03K19/1776 ,  G11C5/02 ,  H03K19/17764 ,  H03K19/17784

CPC classification number: H03K19/1776 ,  G11C5/025 ,  H03K19/17764 ,  H03K19/17784

Abstract: An apparatus includes a data processing array having a plurality of array tiles. Each array tile can include a random-access memory (RAM) having a local memory interface accessible by circuitry within the array tile and an adjacent memory interface accessible by circuitry disposed within an adjacent array tile. Each adjacent memory interface of each array tile can include isolation logic that is programmable to allow the circuitry disposed within the adjacent array tile to access the RAM or prevent the circuitry disposed within the adjacent array tile from accessing the RAM. The data processing array can be subdivided into a plurality of partitions wherein the isolation logic of the adjacent memory interfaces is programmed to prevent array tiles from accessing RAMs across a boundary between the plurality of partitions.

公开(公告)号：US20230376437A1

公开(公告)日：2023-11-23

申请号：US17663824

申请日：2022-05-17

Applicant: Xilinx, Inc.

Inventor： David Patrick Clarke ,  Peter McColgan ,  Juan J. Noguera Serra ,  Tim Tuan ,  Saurabh Mathur ,  Amarnath Kasibhatla ,  Javier Cabezas Rodriguez ,  Pedro Miguel Parola Duarte ,  Zachary Blaise Dickman

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F2213/28

Abstract: An integrated circuit (IC) can include a data processing array including a plurality of compute tiles arranged in a grid. The IC can include an array interface coupled to the data processing array. The array interface includes a plurality of interface tiles. Each interface tile includes a plurality of direct memory access circuits. The IC can include a network-on-chip (NoC) coupled to the array interface. Each direct memory access circuit is communicatively linked to the NoC via an independent communication channel.

公开(公告)号：US20240088900A1

公开(公告)日：2024-03-14

申请号：US18509128

申请日：2023-11-14

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Tim Tuan ,  Javier Cabezas Rodriguez ,  David Clarke ,  Peter McColgan ,  Zachary Blaise Dickman ,  Saurabh Mathur ,  Amarnath Kasibhatla ,  Francisco Barat Quesada

IPC: H03K19/1776 ,  G11C5/02 ,  H03K19/17764 ,  H03K19/17784

CPC classification number: H03K19/1776 ,  G11C5/025 ,  H03K19/17764 ,  H03K19/17784

Abstract: An apparatus includes a data processing array having a plurality of array tiles. The plurality of array tiles include a plurality of compute tiles. The compute tiles include a core coupled to a random-access memory (RAM) in a same compute tile and to a RAM of at least one other compute tile. The data processing array is subdivided into a plurality of partitions. Each partition includes a plurality of array tiles including at least one of the plurality of compute tiles. The apparatus includes a plurality of clock gate circuits being programmable to selectively gate a clock signal provided to a respective one of the plurality of partitions.

公开(公告)号：US20230336179A1

公开(公告)日：2023-10-19

申请号：US17659423

申请日：2022-04-15

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Tim Tuan ,  Javier Cabezas Rodriguez ,  David Clarke ,  Peter McColgan ,  Zachary Blaise Dickman ,  Saurabh Mathur ,  Amarnath Kasibhatla ,  Francisco Barat Quesada

IPC: H03K19/1776 ,  H03K19/17784 ,  H03K19/17764 ,  G11C5/02

CPC classification number: H03K19/1776 ,  H03K19/17784 ,  H03K19/17764 ,  G11C5/025

Abstract: An apparatus includes a data processing array having a plurality of array tiles. Each array tile can include a random-access memory (RAM) having a local memory interface accessible by circuitry within the array tile and an adjacent memory interface accessible by circuitry disposed within an adjacent array tile. Each adjacent memory interface of each array tile can include isolation logic that is programmable to allow the circuitry disposed within the adjacent array tile to access the RAM or prevent the circuitry disposed within the adjacent array tile from accessing the RAM. The data processing array can be subdivided into a plurality of partitions wherein the isolation logic of the adjacent memory interfaces is programmed to prevent array tiles from accessing RAMs across a boundary between the plurality of partitions.