公开(公告)号：US12105716B2

公开(公告)日：2024-10-01

申请号：US15632082

申请日：2017-06-23

Applicant: Xilinx, Inc.

Inventor： Hare K. Verma ,  Sonal Santan ,  Yongjun Wu

IPC: G06F16/00 ,  G06F3/06 ,  G06F9/38 ,  G06F16/245 ,  G06F16/2453 ,  G06F16/2455

CPC classification number: G06F16/24557 ,  G06F3/064 ,  G06F9/3885 ,  G06F16/2453 ,  G06F16/24532 ,  G06F16/24569

Abstract: Embodiments herein describe techniques for preparing and executing tasks related to a database query in a database accelerator. In one embodiment, the database accelerator is separate from a host CPU. A database management system (DBMS) can offload tasks corresponding to a database query to the database accelerator. The DBMS can request data from the database relevant to the query and then convert that data into one or more data blocks that are suitable for processing by the database accelerator. In one embodiment, the database accelerator contains individual hardware processing units (PUs) that can process data in parallel or concurrently. In order to process the data concurrently, the data block includes individual PU data blocks that are each intended for a respective PU in the database accelerator.

公开(公告)号：US20180373760A1

公开(公告)日：2018-12-27

申请号：US15632082

申请日：2017-06-23

Applicant: Xilinx, Inc.

Inventor： Hare K. Verma ,  Sonal Santan ,  Yongjun Wu

IPC: G06F17/30 ,  G06F3/06 ,  G06F9/38

Abstract: Embodiments herein describe techniques for preparing and executing tasks related to a database query in a database accelerator. In one embodiment, the database accelerator is separate from a host CPU. A database management system (DBMS) can offload tasks corresponding to a database query to the database accelerator. The DBMS can request data from the database relevant to the query and then convert that data into one or more data blocks that are suitable for processing by the database accelerator. In one embodiment, the database accelerator contains individual hardware processing units (PUs) that can process data in parallel or concurrently. In order to process the data concurrently, the data block includes individual PU data blocks that are each intended for a respective PU in the database accelerator.

公开(公告)号：US10963460B2

公开(公告)日：2021-03-30

申请号：US16212134

申请日：2018-12-06

Applicant: Xilinx, Inc.

Inventor： Hare K. Verma ,  Bing Tian

IPC: G06F16/00 ,  G06F16/2453 ,  G06F16/2455 ,  G06F9/30

Abstract: Integrated circuits and methods relating to hardware acceleration include independent, programmable, and parallel processing units (PU) custom-adapted to process a data stream and aggregate the results to respond to a query. In an illustrative example, a data stream from a database may be divided into data blocks and allocated to a corresponding PU. Each data block may be processed by one of the PUs to generate results according to a predetermined instruction set. A concatenate unit may merge and concatenate a result of each data block together to generate an output result for the query. In some embodiments, very large database SQL queries, for example, may be accelerated by hardware PU/concatenate engines implemented in fixed ASIC or reconfigurable FPGA hardware circuitry.

公开(公告)号：US10990517B1

公开(公告)日：2021-04-27

申请号：US16259895

申请日：2019-01-28

Applicant: Xilinx, Inc.

Inventor： Hare K. Verma ,  Jiayou Wang ,  Vincent Mirian

IPC: G06F12/02

Abstract: Examples described herein relate to efficient memory access. An example is a system includes a programmable device, and a memory. The programmable device is coupled to the host and receives the read/write requests and the addresses associated therewith. The programmable device interleaves the read/write requests across multiple communication channels based on a subset of bits within each address. The memory receives the read/write requests from the programmable device. The memory stores contents associated with the addresses for write requests and returns contents associated with the addresses for a read request to the programmable device. The programmable device returns the received contents to the host for processing.

公开(公告)号：US20200183937A1

公开(公告)日：2020-06-11

申请号：US16212134

申请日：2018-12-06

Applicant: Xilinx, Inc.

Inventor： Hare K. Verma ,  Bing Tian

IPC: G06F16/2453 ,  G06F16/2455 ,  G06F9/30

Abstract: Integrated circuits and methods relating to hardware acceleration include independent, programmable, and parallel processing units (PU) custom-adapted to process a data stream and aggregate the results to respond to a query. In an illustrative example, a data stream from a database may be divided into data blocks and allocated to a corresponding PU. Each data block may be processed by one of the PUs to generate results according to a predetermined instruction set. A concatenate unit may merge and concatenate a result of each data block together to generate an output result for the query. In some embodiments, very large database SQL queries, for example, may be accelerated by hardware PU/concatenate engines implemented in fixed ASIC or reconfigurable FPGA hardware circuitry.