公开(公告)号：US10990517B1

公开(公告)日：2021-04-27

申请号：US16259895

申请日：2019-01-28

Applicant: Xilinx, Inc.

Inventor： Hare K. Verma ,  Jiayou Wang ,  Vincent Mirian

IPC: G06F12/02

Abstract: Examples described herein relate to efficient memory access. An example is a system includes a programmable device, and a memory. The programmable device is coupled to the host and receives the read/write requests and the addresses associated therewith. The programmable device interleaves the read/write requests across multiple communication channels based on a subset of bits within each address. The memory receives the read/write requests from the programmable device. The memory stores contents associated with the addresses for write requests and returns contents associated with the addresses for a read request to the programmable device. The programmable device returns the received contents to the host for processing.

公开(公告)号：US20230342068A1

公开(公告)日：2023-10-26

申请号：US17660801

申请日：2022-04-26

Applicant: Xilinx, Inc.

Inventor： Sachin Kumawat ,  David K. Liddell ,  Jiayou Wang

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0614 ,  G06F3/0673

Abstract: A system includes a multi-port random-access memory (RAM) configured to store an instruction table. The instruction table specifies a regular expression for application to a data stream. The system includes a regular expression engine configured to process the data stream based on the instruction table. The regular expression engine includes a decoder circuit configured to determine validity of active states output from the RAM, a plurality of active states memories operating concurrently, wherein each active states memory is configured to initiate a read from a different port of the RAM using an address formed of an active state output from the active states memory and a portion of the data stream, and switching circuitry configured to route the active states to the plurality of active states memories according, at least in part, to a load balancing technique and validity of the active states.

公开(公告)号：US12014072B2

公开(公告)日：2024-06-18

申请号：US17660801

申请日：2022-04-26

Applicant: Xilinx, Inc.

Inventor： Sachin Kumawat ,  David K. Liddell ,  Jiayou Wang

IPC: G06F9/44 ,  G06F3/06 ,  G06F11/16

CPC classification number: G06F3/0655 ,  G06F3/0614 ,  G06F3/0673 ,  G06F11/1629 ,  G06F2207/025

Abstract: A system includes a multi-port random-access memory (RAM) configured to store an instruction table. The instruction table specifies a regular expression for application to a data stream. The system includes a regular expression engine configured to process the data stream based on the instruction table. The regular expression engine includes a decoder circuit configured to determine validity of active states output from the RAM, a plurality of active states memories operating concurrently, wherein each active states memory is configured to initiate a read from a different port of the RAM using an address formed of an active state output from the active states memory and a portion of the data stream, and switching circuitry configured to route the active states to the plurality of active states memories according, at least in part, to a load balancing technique and validity of the active states.