公开(公告)号：US11861010B2

公开(公告)日：2024-01-02

申请号：US17651030

申请日：2022-02-14

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Yu Liu ,  Yenpang Lin ,  Lizhi Hou ,  Cheng Zhen ,  Yidong Zhang

IPC: G06F21/64 ,  G06F21/71 ,  G06F21/57 ,  G06F13/16

CPC classification number: G06F21/572 ,  G06F13/1642 ,  G06F13/1663 ,  G06F21/64 ,  G06F21/71

Abstract: An integrated circuit can include a communication endpoint configured to maintain a communication link with a host computer, a queue configured to receive a plurality of host commands from the host computer via the communication link, and a processor configured to execute a device runtime. The processor, responsive to executing the device runtime, is configured to perform validation of the host commands read from the queue and selectively execute the host commands based on a result of the validation on a per host command basis. The host commands are executable by the processor to manage functions of the integrated circuit. The queue is implemented in a region of memory that is shared by the integrated circuit and the host computer.

公开(公告)号：US10956241B1

公开(公告)日：2021-03-23

申请号：US15848691

申请日：2017-12-20

Applicant: Xilinx, Inc.

Inventor： Hem C. Neema ,  Sonal Santan ,  Soren T. Soe ,  Stephen P. Rozum ,  Nik Cimino

IPC: G06F8/41 ,  G06F9/54 ,  G06F21/57 ,  G06F21/53 ,  G06F8/65

Abstract: A computer program product can include a non-transitory computer readable storage medium storing a unified container. The unified container can include a header structure, wherein the header structure has a fixed length and specifies a number of section headers included in the unified container. The unified container can include a plurality of section headers equivalent to the number of section headers specified in the header structure. The unified container can include a plurality of data sections corresponding to the plurality of section headers on a one-to-one basis. The plurality of data sections includes a first data section including a hardware binary and a second data section including a software binary. The hardware binary and the software binary are configured to program a programmable integrated circuit. Each section header specifies a type of data stored in the corresponding data section and specifies a mapping for the corresponding data section.

公开(公告)号：US10922068B1

公开(公告)日：2021-02-16

申请号：US16186204

申请日：2018-11-09

Applicant: Xilinx, Inc.

Inventor： Ryan F. Radjabi ,  Hem C. Neema ,  Sonal Santan ,  Yenpang Lin

IPC: G06F9/44 ,  G06F8/65 ,  G06F13/42

Abstract: Updating firmware in an programmable integrated circuit (IC) includes determining, using a processor of a computer, a base address register (BAR) of an accelerator card from a device data file, wherein the accelerator card includes a programmable IC and is connected to the computer via a communication bus, mapping, using the processor, a feature PROM and a flash programmer circuit of the programmable IC to local memory of the computer using the BAR, and reading, over the communication bus, the feature PROM on the programmable IC to determine a programming mode for programming an external flash memory coupled to the flash programmer circuit. Based on the programming mode and using the processor, firmware is provided to the flash programmer circuit on the programmable IC via the communication bus. The flash programmer circuit is configured to program the firmware into the external flash memory.

公开(公告)号：US09218443B1

公开(公告)日：2015-12-22

申请号：US14539975

申请日：2014-11-12

Applicant: Xilinx, Inc.

Inventor： Henry E. Styles ,  Jeffrey M. Fifield ,  Ralph D. Wittig ,  Philip B. James-Roxby ,  Sonal Santan ,  Devadas Varma ,  Fernando J. Martinez Vallina ,  Sheng Zhou ,  Charles Kwah-Wah Lo

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F8/451

Abstract: OpenCL program compilation may include generating, using a processor, a register transfer level (RTL) description of a first kernel of a heterogeneous, multiprocessor design and integrating the RTL description of the first kernel with a base platform circuit design. The base platform circuit design provides a static interface within a programmable integrated circuit to a host of the heterogeneous, multiprocessor design. A first configuration bitstream may be generated from the RTL description of the first kernel using the processor. The first configuration bitstream specifies a hardware implementation of the first kernel and supporting data for the configuration bitstream. The first configuration bitstream and the supporting data may be included within a binary container.

Abstract translation: OpenCL程序编译可以包括使用处理器来生成异构多处理器设计的第一内核的寄存器传送级（RTL）描述，并将第一内核的RTL描述与基本平台电路设计集成。 基础平台电路设计为可编程集成电路内的静态接口提供了异构多处理器设计的主机。 可以使用处理器从第一内核的RTL描述生成第一配置比特流。 第一配置比特流指定第一内核的硬件实现和配置比特流的支持数据。 第一配置比特流和支持数据可以包括在二进制容器内。

公开(公告)号：US10402223B1

公开(公告)日：2019-09-03

申请号：US15498226

申请日：2017-04-26

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Soren T. Soe

IPC: G06F9/48 ,  G06F13/22 ,  G06F13/28 ,  G06F13/16

Abstract: A heterogeneous computing system can include a host memory and a host processor. The host memory is configured to maintain a write task queue and a read task queue. The host processor is coupled to the host memory and a processing device. The host processor is adapted to store write tasks in the write task queue. The write tasks cause transfer of input data to the processing device. The processing device is adapted to perform offloaded functions. The host processor is adapted to store read tasks in the read task queue. The read tasks cause transfer of results from the offloaded functions from the processing device. The host processor is further adapted to maintain a number of direct memory access (DMA) worker threads corresponding to concurrent data transfer capability of the processing device. Each DMA worker thread is preconfigured to execute tasks from the write task queue or the read task queue.

公开(公告)号：US10216217B1

公开(公告)日：2019-02-26

申请号：US15382390

申请日：2016-12-16

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Sudipto Chakraborty ,  Fei Rui ,  Stephen P. Rozum ,  Yenpang Lin ,  Yau-Tsun S. Li ,  Sumit Roy

IPC: G06F1/00 ,  G06F1/08

Abstract: Hardware acceleration for a kernel can include selecting, using a processor, a kernel, determining, using the processor, a clock frequency for the selected kernel, and programming, using the processor, a clock circuit to generate a clock signal having a clock frequency compatible with the clock frequency of the selected kernel. Using the processor, the selected kernel can be implemented as a kernel circuit within a region of programmable circuitry. The kernel circuit can be clocked using the clock signal from the clock circuit having the compatible clock frequency.

公开(公告)号：US09864828B1

公开(公告)日：2018-01-09

申请号：US14857634

申请日：2015-09-17

Applicant: Xilinx, Inc.

Inventor： Susheel Kumar Puthana ,  Stephen P. Rozum ,  Sudipto Chakraborty ,  David A. Knol ,  Yong Li ,  Fernando J. Martinez Vallina ,  Sonal Santan ,  Nabeel Shirazi ,  Salil R. Raje ,  Ethan T. Parker ,  Suman Kumar Timmireddy ,  Heera Nand

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5072

Abstract: Implementing hardware accelerators using programmable integrated circuits may include performing, using a processor, a design flow on a static circuit design. The static circuit design may specify a region reserved for a hardware accelerator and a static region comprising interface circuitry configured to couple the hardware accelerator with an external node. The design flow may generate an implemented static circuit design. Metadata describing the interface circuitry may be generated using a processor. A device support archive including the implemented static circuit design and the metadata may be written, using the processor, to a computer readable storage medium.

公开(公告)号：US09846660B2

公开(公告)日：2017-12-19

申请号：US14539985

申请日：2014-11-12

Applicant: Xilinx, Inc.

Inventor： Henry E. Styles ,  Jeffrey M. Fifield ,  Ralph D. Wittig ,  Philip B. James-Roxby ,  Sonal Santan ,  Devadas Varma ,  Fernando J. Martinez Vallina ,  Sheng Zhou ,  Charles Kwok-Wah Lo

IPC: G06F13/12 ,  G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1689 ,  G06F13/28

Abstract: An integrated circuit (IC) includes a first region being static and providing an interface between the IC and a host processor. The first region includes a first interconnect circuit block having a first master interface and a second interconnect circuit block having a first slave interface. The IC includes a second region coupled to the first region. The second region implements a kernel of a heterogeneous, multiprocessor design and includes a slave interface coupled to the first master interface of the first interconnect circuit block and configured to receive commands from the host processor. The second region also includes a master interface coupled the first slave interface of the second interconnect circuit block, wherein the master interface of the second region is a master for a memory controller.

公开(公告)号：US12105716B2

公开(公告)日：2024-10-01

申请号：US15632082

申请日：2017-06-23

Applicant: Xilinx, Inc.

Inventor： Hare K. Verma ,  Sonal Santan ,  Yongjun Wu

IPC: G06F16/00 ,  G06F3/06 ,  G06F9/38 ,  G06F16/245 ,  G06F16/2453 ,  G06F16/2455

CPC classification number: G06F16/24557 ,  G06F3/064 ,  G06F9/3885 ,  G06F16/2453 ,  G06F16/24532 ,  G06F16/24569

Abstract: Embodiments herein describe techniques for preparing and executing tasks related to a database query in a database accelerator. In one embodiment, the database accelerator is separate from a host CPU. A database management system (DBMS) can offload tasks corresponding to a database query to the database accelerator. The DBMS can request data from the database relevant to the query and then convert that data into one or more data blocks that are suitable for processing by the database accelerator. In one embodiment, the database accelerator contains individual hardware processing units (PUs) that can process data in parallel or concurrently. In order to process the data concurrently, the data block includes individual PU data blocks that are each intended for a respective PU in the database accelerator.

公开(公告)号：US11474555B1

公开(公告)日：2022-10-18

申请号：US15684035

申请日：2017-08-23

Applicant: Xilinx, Inc.

Inventor： Hem C. Neema ,  Sonal Santan ,  Julian M. Kain ,  Stephen P. Rozum ,  Khang K. Dao ,  Kyle Corbett

IPC: G06F1/10 ,  G06F13/10 ,  G06F13/28 ,  G06F13/16 ,  G06F13/40

Abstract: An example computing system includes: a processing system, a hardware accelerator coupled to the processing system, and a software platform executing on the processing system. The hardware accelerator includes: a programmable integrated circuit (IC) configured with an acceleration circuit having a static region and a programmable region; a memory in the programmable IC configured to store metadata describing interface circuitry in at least one of the static region and the programmable region of the acceleration circuit. The software platform includes program code executable by the processing system to read the metadata from the memory of the hardware accelerator.