公开(公告)号：US20210011172A1

公开(公告)日：2021-01-14

申请号：US16506064

申请日：2019-07-09

Applicant: Xilinx, Inc.

Inventor： Brendan Farley ,  John K. Jennings ,  John G. O'Dwyer

IPC: G01S19/23 ,  H03M1/10 ,  H03K19/173 ,  G01R31/3185 ,  G01R31/3167

Abstract: Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect. The interconnect system may include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors, and may include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor as data packets.

公开(公告)号：US10110202B1

公开(公告)日：2018-10-23

申请号：US15451778

申请日：2017-03-07

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide ,  John G. O'Dwyer

IPC: H03K3/011 ,  H03K5/15 ,  H03K5/19 ,  H03K5/00

Abstract: An apparatus for clock deskew includes: a first delay element configured to receive a clock signal from a clock, wherein the delay element comprises multiple delay lines; a first multiplexer coupled to the multiple delay lines; a sensor configured to sense a voltage, a temperature, or both, and to provide a sensor output based at least on the sensed voltage and/or the sensed temperature; and a converter configured to receive the sensor output, and to generate a converted signal; wherein the first multiplexer is configured to provide a delay line output from one of the multiple delay lines based at least in part on the converted signal.