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公开(公告)号：US11003204B1
公开(公告)日：2021-05-11
申请号：US16216990
申请日：2018-12-11
申请人： Xilinx, Inc.
发明人： Ionut C. Cical , Edward Cullen , Brendan Farley
IPC分类号： G06F1/08 , G06F1/324 , H03K3/0231 , H03K3/011 , G06F1/3296 , H03B5/12 , H03L7/099
摘要： Examples described herein provide for a relaxation oscillator and corresponding methods of operation. In an example, a circuit includes a dynamically controllable current source, a capacitor, and an oscillator generation circuit. The dynamically controllable current source includes a digitally tunable current mirror configured to generate a current. The digitally tunable current mirror includes multiple transistors configured to be selectively electrically connected in parallel to alter a gain of the digitally tunable current mirror to control the current. The capacitor is selectively electrically connected to the dynamically controllable current source. The oscillator generation circuit is electrically connected to the capacitor. The oscillator generation circuit is configured to generate an oscillation signal in response to a voltage of the capacitor.
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公开(公告)号：US10404265B1
公开(公告)日：2019-09-03
申请号：US16117650
申请日：2018-08-30
申请人： Xilinx, Inc.
发明人： Brendan Farley , Bruno Miguel Vaz , Darragh Walsh
摘要： An example apparatus includes a first transistor coupled between a supply node and a first node, a current mirror having a first side and a second side, and a second transistor coupled between the first node and the first side of the current mirror. The input buffer further includes a third transistor coupled between the first node and the second side of the current mirror, and a first capacitor coupled between a source and a drain of the second transistor.
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公开(公告)号：US11605886B1
公开(公告)日：2023-03-14
申请号：US17133518
申请日：2020-12-23
申请人： XILINX, INC.
发明人： Gamal Refai-Ahmed , Chi-Yi Chao , Lik Tsang , Jens Weis , Brendan Farley , Anthony Torza , Suresh Ramalingam
IPC分类号： H01Q1/42 , H01L23/427 , H01Q1/02
摘要： An antenna assembly is provided having passive cooling elements that enable compact design. In one example, an antenna assembly is provided that includes a heat sink assembly having an interior side and an exterior side, an antenna array, an antenna circuit board, and a radome. The antenna circuit board includes at least one integrated circuit (IC) die. The IC die has a conductive primary heat dissipation path to the interior side of the heat sink assembly. The radome is coupled to the heat sink assembly and encloses the antenna circuit board and the antenna array between the radome and the heat sink assembly. The heat sink assembly includes a metal base plate and at least a first heat pipe embedded with the metal base plate. The first heat pipe is disposed between the metal base plate and the IC die.
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4.发明授权公开(公告)号：US10530379B1
公开(公告)日：2020-01-07
申请号：US16283692
申请日：2019-02-22
申请人： Xilinx, Inc.
发明人： Bruno Miguel Vaz , Brendan Farley
摘要： An analog-to-digital converter (ADC) circuit (400) and method of operation are disclosed. In some aspects, the ADC circuit (400) may include a plurality of channels (500), a gain calibration circuit (420), and a time-skew calibration circuit (430). Each of the plurality of channels (500) may include an ADC (520), a switch (510) configured to provide a differential input signal to the ADC (520), a calibration device (530), a multiplier (540), and a pseudorandom bit sequence (PRBS) circuit (550) to provide a pseudorandom number (PN) to the switch (510), to the calibration device (530), and to the multiplier (540). In some embodiments, the calibration device (530) may include first and second offset calibration circuits (531-532) coupled in parallel between a de-multiplexer (D1) and a multiplexer (M1) that alternately route signals to the first and second offset calibration circuits (531-532) based on the pseudorandom number (PN).
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公开(公告)号：US11569820B2
公开(公告)日：2023-01-31
申请号：US17709164
申请日：2022-03-30
申请人： XILINX, INC.
发明人： John Edward McGrath , Woon Wong , John O'Dwyer , Paul Newson , Brendan Farley
IPC分类号： H03K19/1776
摘要： An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.
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公开(公告)号：US11009597B2
公开(公告)日：2021-05-18
申请号：US16222801
申请日：2018-12-17
申请人： Xilinx, Inc.
摘要： A radar system includes a transmitter to transmit a sequence of pulses, a receiver to receive reflections of the transmitted pulses, and velocity detection circuitry to determine a velocity of an object in a path of the transmitted pulses based at least in part on the transmitted pulses and the reflected pulses. The transmitter includes a plurality of digital-to-analog converters (DACs) to generate the sequence of pulses in response to a clock signal. The receiver includes a plurality of analog-to-digital converters (ADCs) to sample the reflected pulses in response to the clock signal. Accordingly, the ADCs are locked in phase with the DACs.
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公开(公告)号：US10826517B1
公开(公告)日：2020-11-03
申请号：US16680356
申请日：2019-11-11
申请人： Xilinx, Inc.
发明人： Bruno Miguel Vaz , John E. McGrath , Conrado K. Mesadri , Woon C. Wong , Ali Boumaalif , Christopher Erdman , Brendan Farley
IPC分类号： H03M1/12 , H03M1/10 , G01R31/3185 , H04L12/43 , H04L12/433
摘要： An integrated circuit is described. The integrated circuit comprises an analog-to-digital converter circuit configured to receive an input signal at an input and generate an output signal at an output; and a monitor circuit coupled to the output of the analog-to-digital converter circuit, the monitor circuit configured to receive the output signal and to generate integration coefficients for the analog-to-digital converter circuit; wherein the integration coefficients are dynamically generated based upon signal characteristics of the output signal generated by the analog-to-digital converter circuit. A method of receiving data in an integrated circuit is also described.
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公开(公告)号：US20150002326A1
公开(公告)日：2015-01-01
申请号：US13928798
申请日：2013-06-27
申请人： Xilinx, Inc.
发明人： Brendan Farley , James Hudner , Ivan Bogue , Declan Carey , Darragh Walsh , Marc Erett
IPC分类号： H03M1/12
摘要： An analog-to-digital converter (“ADC”) is disclosed. The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.
摘要翻译： 公开了一种模拟 - 数字转换器（“ADC”）。 ADC包括一组比较器和一个窗口控制器。 窗口控制器耦合到比较器组，以选择性地激活与窗口大小相关联的比较器组的第一比较器，并且选择性地使比较器组的第二比较器失活。
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公开(公告)号：US11777503B2
公开(公告)日：2023-10-03
申请号：US17453310
申请日：2021-11-02
申请人： XILINX, INC.
发明人： John Edward McGrath , Woon Wong , John O'Dwyer , Paul Newson , Brendan Farley
IPC分类号： H03K19/1776
CPC分类号： H03K19/1776
摘要： An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.
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公开(公告)号：US20210011172A1
公开(公告)日：2021-01-14
申请号：US16506064
申请日：2019-07-09
申请人： Xilinx, Inc.
IPC分类号： G01S19/23 , H03M1/10 , H03K19/173 , G01R31/3185 , G01R31/3167
摘要： Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect. The interconnect system may include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors, and may include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor as data packets.
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