公开(公告)号：US10699053B1

公开(公告)日：2020-06-30

申请号：US15873724

申请日：2018-01-17

Applicant: Xilinx, Inc.

Inventor： Zhiyong Wang ,  Ruibing Lu ,  Lin Chai ,  Sabyasachi Das

IPC: G06F30/398 ,  G06F30/34 ,  G06F30/392 ,  G06F30/394 ,  G06F30/3312 ,  G06F30/39 ,  G06F30/327 ,  G06F119/12

Abstract: Methods and apparatus for implementing a circuit design are provided. A physical description is generated corresponding to a predefined physical layout of a programmable integrated circuit. The circuit design includes a memory block. A timing analysis is executed to determine a first timing profile of the physical description. The physical description is optimized (or at least altered), and a physical implementation is generated based on the optimized physical description. Optimizing the physical description includes: selectively moving from or into the memory block of the physical description a register in response to an attribute of the memory block; executing a timing analysis to determine a second timing profile of the physical description with the register moved from or into the memory block of the physical description; comparing the first and second timing profiles; and selectively accepting or reversing the moving based on the comparison of the first and second timing profiles.