公开(公告)号：US11373024B1

公开(公告)日：2022-06-28

申请号：US16353981

申请日：2019-03-14

Applicant: Xilinx, Inc.

Inventor： Sahil Goyal ,  Hongbin Zheng ,  Mahesh Attarde ,  Amit Kasat

IPC: G06F30/33 ,  G06F30/331

Abstract: The disclosed approaches involve executing simulator-parallel processes that correspond to states of a finite state machine representation of a circuit design. Execution of each simulator-parallel process is initiated in response to an event generated by another one of the simulator-parallel processes. A data access transaction of the circuit design is simulated by calling a first function of a wrapper from a first process of the simulator-parallel processes. The first process waits for an estimated number of simulation clock cycles. The estimated number of simulation clock cycles represents an actual time period required to complete an actual data access transaction.

公开(公告)号：US12032932B2

公开(公告)日：2024-07-09

申请号：US17811660

申请日：2022-07-11

Applicant: Xilinx, Inc.

Inventor： Shantanu Mishra ,  Hemant Kashyap ,  Uday Kyatham ,  Mahesh Attarde ,  Amit Kasat Kasat

IPC: G06F8/41

CPC classification number: G06F8/434 ,  G06F8/44

Abstract: Compiling a high-level synthesis circuit design for simulation includes analyzing, using computer hardware, a kernel specified in a high-level language to detect pointers therein. A determination is made as to which of the pointers are global address space pointers referencing a global address space. The kernel is instrumented by replacing accesses in the kernel to the global address space with calls to wrapper functions for performing the accesses. A simulation kernel is generated that specifies an assembly language version of the kernel as instrumented.

公开(公告)号：US20240012629A1

公开(公告)日：2024-01-11

申请号：US17811660

申请日：2022-07-11

Applicant: Xilinx, Inc.

Inventor： Shantanu Mishra ,  Hemant Kashyap ,  Uday Kyatham ,  Mahesh Attarde ,  Amit Kasat Kasat

IPC: G06F8/41

CPC classification number: G06F8/434 ,  G06F8/44

Abstract: Compiling a high-level synthesis circuit design for simulation includes analyzing, using computer hardware, a kernel specified in a high-level language to detect pointers therein. A determination is made as to which of the pointers are global address space pointers referencing a global address space. The kernel is instrumented by replacing accesses in the kernel to the global address space with calls to wrapper functions for performing the accesses. A simulation kernel is generated that specifies an assembly language version of the kernel as instrumented.