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公开(公告)号：US20230113197A1
公开(公告)日：2023-04-13
申请号：US17498048
申请日：2021-10-11
Applicant: Xilinx, Inc.
Inventor： Amit Kasat , Tharun Kumar Ksheerasagar , Hemant Kashyap , Madhusudana Reddy , Rohit Bhadana
IPC: G06F30/3308 , G06F30/323
Abstract: Computer-based simulation of a device under test (DUT) corresponding to a user circuit design includes providing an adapter configured to couple to the DUT during the computer-based simulation (simulation). The adapter is configured to translate incoming high-level programming language (HLPL) transactions into DUT compatible data for conveyance to the DUT and translate DUT compatible data generated by the DUT to outgoing HLPL transactions. A communication server is provided that couples to the adapter during the simulation. The communication server is configured to exchange the incoming and outgoing HLPL transactions with an entity executing external to the simulation. A communication layer client is provided that is configured to execute external to the simulation and exchange the incoming and outgoing HLPL transactions with the communication server. The communication layer client provides an application programming interface through which an external computer program generates data traffic to drive the DUT within the simulation.
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公开(公告)号：US10437946B1
公开(公告)日：2019-10-08
申请号：US15255013
申请日：2016-09-01
Applicant: Xilinx, Inc.
Inventor： Amit Kasat , Shreegopal S. Agrawal , Venkat Prasad Aleti
IPC: G06F17/50
Abstract: Using pin planning for core sources includes identifying, using a processor, a first pin configuration and a second pin configuration for a core source of a behavioral description of a circuit design. The second pin configuration is generated by a pin planning operation. The first pin configuration of the core source can be compared with the second pin configuration of the core source using a processor. Responsive to detecting a difference between the first pin configuration and the second pin configuration, the core source can be automatically update, using the processor, based upon the second pin configuration.
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公开(公告)号：US20240184616A1
公开(公告)日：2024-06-06
申请号：US18075731
申请日：2022-12-06
Applicant: Xilinx, Inc.
Inventor： Tharun Kumar Ksheerasagar , Hemant Kashyap , Amit Kasat , Meghana Tripathi , Shantanu Mishra
Abstract: A thread manager creates multiple threads by to execute a simulation of subsystems of a system-on-chip on multiple processor cores in response to execution of a simulation program. The threads execute multiple cycle-accurate simulation models of the subsystems in parallel in an execution phase of each simulation cycle of a plurality of simulation cycles of the simulation. The threads update interfaces of the simulation models in an update phase of each simulation cycle of the plurality of simulation cycles.
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公开(公告)号：US11373024B1
公开(公告)日：2022-06-28
申请号：US16353981
申请日：2019-03-14
Applicant: Xilinx, Inc.
Inventor： Sahil Goyal , Hongbin Zheng , Mahesh Attarde , Amit Kasat
IPC: G06F30/33 , G06F30/331
Abstract: The disclosed approaches involve executing simulator-parallel processes that correspond to states of a finite state machine representation of a circuit design. Execution of each simulator-parallel process is initiated in response to an event generated by another one of the simulator-parallel processes. A data access transaction of the circuit design is simulated by calling a first function of a wrapper from a first process of the simulator-parallel processes. The first process waits for an estimated number of simulation clock cycles. The estimated number of simulation clock cycles represents an actual time period required to complete an actual data access transaction.
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5.发明授权公开(公告)号：US10481814B1
公开(公告)日：2019-11-19
申请号：US15635646
申请日：2017-06-28
Applicant: Xilinx, Inc.
Inventor： Heera Nand , Amit Kasat
Abstract: Implementing a kernel as circuitry in an integrated circuit can include determining, using a processor, memory access operations and work operations from kernel program code and generating, using the processor, a circuit design from the kernel program code. The circuit design implements a circuit architecture having a memory access circuit configured to perform the memory access operations and an execution circuit configured to perform the work operations concurrently with the memory access operations.
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Patent Agency Ranking
公开(公告)号：US11630935B1
公开(公告)日：2023-04-18
申请号：US17498048
申请日：2021-10-11
Applicant: Xilinx, Inc.
Inventor： Amit Kasat , Tharun Kumar Ksheerasagar , Hemant Kashyap , Madhusudana Reddy , Rohit Bhadana
IPC: G06F30/30 , G01R31/28 , G06F30/3308 , G06F30/323 , G01R31/3183
Abstract: Computer-based simulation of a device under test (DUT) corresponding to a user circuit design includes providing an adapter configured to couple to the DUT during the computer-based simulation (simulation). The adapter is configured to translate incoming high-level programming language (HLPL) transactions into DUT compatible data for conveyance to the DUT and translate DUT compatible data generated by the DUT to outgoing HLPL transactions. A communication server is provided that couples to the adapter during the simulation. The communication server is configured to exchange the incoming and outgoing HLPL transactions with an entity executing external to the simulation. A communication layer client is provided that is configured to execute external to the simulation and exchange the incoming and outgoing HLPL transactions with the communication server. The communication layer client provides an application programming interface through which an external computer program generates data traffic to drive the DUT within the simulation.
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公开(公告)号：US11281834B1
公开(公告)日：2022-03-22
申请号：US16531346
申请日：2019-08-05
Applicant: Xilinx, Inc.
Inventor： Rajvinder S. Klair , Alec J. Wong , Sahil Goyal , Amit Kasat , Brian Cotter , Herve Alexanian
Abstract: Approaches for protection of HLL simulation models in a circuit design having unprotected high-level language (HLL) program code and first metadata of a shared library of executable simulation models that are based on sensitive HLL simulation models. A design tool determines a first storage location of the shared library based on the first metadata and compiles the unprotected HLL program code into an executable object. The design tool links the executable object with the library of executable simulation models from the first storage location and then simulates the circuit design by executing the executable object and loading the executable simulation models in response to initiation by the executable object.
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公开(公告)号：US08595684B1
公开(公告)日：2013-11-26
申请号：US13796702
申请日：2013-03-12
Applicant: Xilinx, Inc.
Inventor： Shay P. Seng , Amit Kasat
CPC classification number: G06F17/5045 , G06F2217/06
Abstract: A method is provided for generation of a circuit design. A set of design assistance rules is retrieved from a database. Each design assistance rule in the set includes a list of design objects to which the design assistance rule applies, a set of criteria to be satisfied by the circuit design before the design assistance rule may be applied, a set of configuration options, and an executable script configured to perform an automated configuration of the circuit design. In response to a change in the circuit design, applicable design assistance rules are determined based on the corresponding sets of criteria. In response to determining that one or more design assistance rules are applicable, data indicating that the one or more design assistance rules are available is output. In response to input that selects a design assistance rule the executable script corresponding to the selected design assistance rule is executed.
Abstract translation: 提供了一种用于产生电路设计的方法。 从数据库中检索一组设计辅助规则。 该集合中的每个设计辅助规则包括设计辅助规则所适用的设计对象的列表，可以应用设计辅助规则之前由电路设计满足的一组标准，一组配置选项和可执行文件 脚本被配置为执行电路设计的自动配置。 响应于电路设计的变化，可以基于相应的标准集来确定适用的设计辅助规则。 响应于确定可以使用一个或多个设计辅助规则，输出指示一个或多个设计辅助规则可用的数据。 响应于选择设计辅助规则的输入，执行与所选择的设计辅助规则相对应的可执行脚本。
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公开(公告)号：US10691580B1
公开(公告)日：2020-06-23
申请号：US15825991
申请日：2017-11-29
Applicant: Xilinx, Inc.
Inventor： Amit Kasat , Ch Vamshi Krishna , Sahil Goyal
IPC: G06F11/36 , G06F30/331 , G06F9/455
Abstract: Diagnosing applications that use hardware acceleration can include emulating, using a processor, a kernel designated for hardware acceleration by executing a device program binary implementing a register transfer level simulator for the kernel. The device program binary is executed in coordination with a host binary and a static circuitry binary. During the emulation, error conditions may be detected using diagnostic program code of the static circuitry binary. The error conditions may relate to memory access violations or kernel deadlocks. A notification of error conditions may be output.
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公开(公告)号：US10180850B1
公开(公告)日：2019-01-15
申请号：US14931071
申请日：2015-11-03
Applicant: Xilinx, Inc.
Inventor： Amit Kasat , Nikhil A. Dhume , Sahil Goyal , Ch Vamshi Krishna
Abstract: Emulating a heterogeneous application having a kernel designated for hardware acceleration may include compiling, using a processor, host program code into a host binary configured to execute in a first process of a computing system and generating, using the processor, a device program binary implementing a register transfer level simulator using the kernel. The device program binary may be configured to execute in a second, different process of the computing system. A high level programming language model of static circuitry of a programmable integrated circuit that couples to a circuit implementation of the kernel may be compiled into a static circuitry binary. The static circuitry binary may be used by the register transfer level simulator during emulation.
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