公开(公告)号：US11373024B1

公开(公告)日：2022-06-28

申请号：US16353981

申请日：2019-03-14

Applicant: Xilinx, Inc.

Inventor： Sahil Goyal ,  Hongbin Zheng ,  Mahesh Attarde ,  Amit Kasat

IPC: G06F30/33 ,  G06F30/331

Abstract: The disclosed approaches involve executing simulator-parallel processes that correspond to states of a finite state machine representation of a circuit design. Execution of each simulator-parallel process is initiated in response to an event generated by another one of the simulator-parallel processes. A data access transaction of the circuit design is simulated by calling a first function of a wrapper from a first process of the simulator-parallel processes. The first process waits for an estimated number of simulation clock cycles. The estimated number of simulation clock cycles represents an actual time period required to complete an actual data access transaction.

公开(公告)号：US11539770B1

公开(公告)日：2022-12-27

申请号：US17201172

申请日：2021-03-15

Applicant: Xilinx, Inc.

Inventor： Heera Nand ,  Sahil Goyal

IPC: H04L65/61 ,  G06F30/392 ,  G06F111/02

Abstract: Providing host-to-kernel streaming support can include determining a platform circuitry for use with a streaming kernel of a circuit design. The streaming kernel is configured for implementation in a user circuitry region of an integrated circuit (IC) to perform tasks offloaded from a host computer. The platform circuitry is configured for implementation in a static circuitry region of the IC. The platform circuitry is configured to establish a communication link with the host computer. An adaptable streaming controller can be inserted within the circuit design. The adaptable streaming controller is configured for implementation in the user circuitry region and connects to the streaming kernel. The adaptable streaming controller further communicatively links the streaming kernel with the platform circuitry. The adaptable streaming controller can be parameterized for exchanging data between the platform circuitry and the streaming kernel based, at least in part, on a type of the platform circuitry.

公开(公告)号：US11281834B1

公开(公告)日：2022-03-22

申请号：US16531346

申请日：2019-08-05

Applicant: Xilinx, Inc.

Inventor： Rajvinder S. Klair ,  Alec J. Wong ,  Sahil Goyal ,  Amit Kasat ,  Brian Cotter ,  Herve Alexanian

IPC: G06F30/36 ,  G06F30/367 ,  G06F8/41 ,  G06F8/70 ,  G06F21/60 ,  G06F9/445 ,  G06F8/54

Abstract: Approaches for protection of HLL simulation models in a circuit design having unprotected high-level language (HLL) program code and first metadata of a shared library of executable simulation models that are based on sensitive HLL simulation models. A design tool determines a first storage location of the shared library based on the first metadata and compiles the unprotected HLL program code into an executable object. The design tool links the executable object with the library of executable simulation models from the first storage location and then simulates the circuit design by executing the executable object and loading the executable simulation models in response to initiation by the executable object.

公开(公告)号：US10691580B1

公开(公告)日：2020-06-23

申请号：US15825991

申请日：2017-11-29

Applicant: Xilinx, Inc.

Inventor： Amit Kasat ,  Ch Vamshi Krishna ,  Sahil Goyal

IPC: G06F11/36 ,  G06F30/331 ,  G06F9/455

Abstract: Diagnosing applications that use hardware acceleration can include emulating, using a processor, a kernel designated for hardware acceleration by executing a device program binary implementing a register transfer level simulator for the kernel. The device program binary is executed in coordination with a host binary and a static circuitry binary. During the emulation, error conditions may be detected using diagnostic program code of the static circuitry binary. The error conditions may relate to memory access violations or kernel deadlocks. A notification of error conditions may be output.

公开(公告)号：US10180850B1

公开(公告)日：2019-01-15

申请号：US14931071

申请日：2015-11-03

Applicant: Xilinx, Inc.

Inventor： Amit Kasat ,  Nikhil A. Dhume ,  Sahil Goyal ,  Ch Vamshi Krishna

IPC: G06F17/50 ,  G06F7/62 ,  G06F9/455

Abstract: Emulating a heterogeneous application having a kernel designated for hardware acceleration may include compiling, using a processor, host program code into a host binary configured to execute in a first process of a computing system and generating, using the processor, a device program binary implementing a register transfer level simulator using the kernel. The device program binary may be configured to execute in a second, different process of the computing system. A high level programming language model of static circuitry of a programmable integrated circuit that couples to a circuit implementation of the kernel may be compiled into a static circuitry binary. The static circuitry binary may be used by the register transfer level simulator during emulation.