-
公开(公告)号：US20200293635A1
公开(公告)日：2020-09-17
申请号：US16299575
申请日：2019-03-12
Applicant: Xilinx, Inc.
Inventor： Brian S. Martin , Premduth Vidyanandan , Mark B. Carson , Neil Watson , Gary J. McClintock
Abstract: An example hardware accelerator for a computer system includes a programmable device and further includes kernel logic configured in a programmable fabric of the programmable device, and an intellectual property (IP) checker circuit in the kernel logic. The IP checker circuit is configured to obtain a device identifier (ID) of the programmable device and a signed whitelist, the signed whitelist including a list of device IDs and a signature, verify the signature of the signed whitelist, compare the device ID against the list of device IDs, and selectively assert or deassert an enable of the kernel logic in response to presence or absence, respectively, of the device ID in the list of device IDs and verification of the signature.
-
公开(公告)号：US10608641B2
公开(公告)日：2020-03-31
申请号：US16041602
申请日：2018-07-20
Applicant: Xilinx, Inc.
Inventor： Hao Yu , Raymond Kong , Brian S. Martin , Jun Liu
IPC: G06F17/50 , G06F15/78 , H03K19/17756 , H03K19/1776 , H03K19/17736 , H03K19/17728 , H03K19/177
Abstract: Hierarchical partial reconfiguration for integrated circuits includes converting, using computer hardware, a first partial reconfiguration module of a circuit design into a first partial reconfiguration container, wherein the circuit design is placed and routed, loading, using the computer hardware, a first netlist into the first partial reconfiguration container, wherein the first netlist includes a first plurality of partial reconfiguration modules that are initially empty, and including, using the computer hardware, a further netlist within each of the first plurality of partial reconfiguration modules. Using the computer hardware, the first partial reconfiguration container is implemented with the first plurality of partial reconfiguration modules being implemented within the first partial reconfiguration container.
-
公开(公告)号：US11449347B1
公开(公告)日：2022-09-20
申请号：US16421367
申请日：2019-05-23
Applicant: Xilinx, Inc.
Inventor： Raymond Kong , Brian S. Martin , Hao Yu , Jun Liu , Ashish Sirasao
Abstract: Time-multiplexing implementation of hardware accelerated functions includes associating each function of a plurality of functions from program code with an accelerator binary image specifying a hardware accelerated version of the associated function and determining which accelerator binary images are data independent. Using the computer hardware, the accelerator binary images can be scheduled for implementation in a programmable integrated circuit within each of a plurality of partial reconfiguration regions based on data independence.
-
公开(公告)号：US11144652B1
公开(公告)日：2021-10-12
申请号：US16721550
申请日：2019-12-19
Applicant: Xilinx, Inc.
Inventor： Ellery Cochell , Brian S. Martin , Ravi N. Kurlagunda
Abstract: Secure updating of programmable integrated circuits includes receiving, within the programmable integrated circuit, a configuration bitstream, inserting, using a processor of the programmable integrated circuit, a key into the configuration bitstream resulting in a modified configuration bitstream, encrypting, using the programmable integrated circuit, the modified configuration bitstream using the key resulting in an encrypted configuration bitstream, and storing the encrypted configuration bitstream in a boot memory for the programmable integrated circuit.
-
公开(公告)号：US20200293636A1
公开(公告)日：2020-09-17
申请号：US16299611
申请日：2019-03-12
Applicant: Xilinx, Inc.
Inventor： Brian S. Martin , Premduth Vidyanandan , Mark B. Carson , Neil Watson , Gary J. McClintock
Abstract: An example hardware accelerator for a computer system includes a programmable device and further includes kernel logic configured in a first programmable fabric of the programmable device, a shell circuit configured in a second programmable fabric of the programmable device, the shell circuit configured to provide an interface between a computer system and the kernel logic, and an intellectual property (IP) checker circuit in the kernel logic The IP checker circuit is configured to obtain a device identifier (ID) from the first programmable fabric and a signed whitelist, the signed whitelist including a list of device IDs and a signature, verify the signature of the signed whitelist, compare the device ID against the list of device IDs, and selectively assert or deassert an enable of the kernel logic in response to presence or absence, respectively, of the device ID in the list of device IDs and verification of the signature.
-
Patent Agency Ranking
公开(公告)号：US11294992B2
公开(公告)日：2022-04-05
申请号：US16299611
申请日：2019-03-12
Applicant: Xilinx, Inc.
Inventor： Brian S. Martin , Premduth Vidyanandan , Mark B. Carson , Neil Watson , Gary J. McClintock
Abstract: An example hardware accelerator for a computer system includes a programmable device and further includes kernel logic configured in a first programmable fabric of the programmable device, a shell circuit configured in a second programmable fabric of the programmable device, the shell circuit configured to provide an interface between a computer system and the kernel logic, and an intellectual property (IP) checker circuit in the kernel logic The IP checker circuit is configured to obtain a device identifier (ID) from the first programmable fabric and a signed whitelist, the signed whitelist including a list of device IDs and a signature, verify the signature of the signed whitelist, compare the device ID against the list of device IDs, and selectively assert or deassert an enable of the kernel logic in response to presence or absence, respectively, of the device ID in the list of device IDs and verification of the signature.
-
公开(公告)号：US11055106B1
公开(公告)日：2021-07-06
申请号：US16719449
申请日：2019-12-18
Applicant: Xilinx, Inc.
Inventor： Ellery Cochell , Brian S. Martin , Chandrasekhar S. Thyamagondlu , Ravi N. Kurlagunda
IPC: G06F9/4401 , G06F21/57 , G06F13/28
Abstract: Bootstrapping a programmable integrated circuit (IC) based network interface card (NIC) can include implementing, within the programmable IC, a first circuitry by loading a first stage configuration bitstream, wherein the first circuitry includes a bus endpoint configured to communicate with a host computer via a communication bus, a platform processor, and a first bootloader. The platform processor, executing the first bootloader, loads a first firmware within the programmable IC. A second circuitry is implemented within the programmable IC by the platform processor executing the first firmware to load a second stage configuration bitstream. The second circuitry includes a NIC controller. The platform processor, executing the first firmware, loads a second firmware within the programmable IC. The second firmware is executable to configure the second circuitry.
-
公开(公告)号：US20200028511A1
公开(公告)日：2020-01-23
申请号：US16041602
申请日：2018-07-20
Applicant: Xilinx, Inc.
Inventor： Hao Yu , Raymond Kong , Brian S. Martin , Jun Liu
IPC: H03K19/177 , G06F17/50
Abstract: Hierarchical partial reconfiguration for integrated circuits includes converting, using computer hardware, a first partial reconfiguration module of a circuit design into a first partial reconfiguration container, wherein the circuit design is placed and routed, loading, using the computer hardware, a first netlist into the first partial reconfiguration container, wherein the first netlist includes a first plurality of partial reconfiguration modules that are initially empty, and including, using the computer hardware, a further netlist within each of the first plurality of partial reconfiguration modules. Using the computer hardware, the first partial reconfiguration container is implemented with the first plurality of partial reconfiguration modules being implemented within the first partial reconfiguration container.
-
公开(公告)号：US11507394B1
公开(公告)日：2022-11-22
申请号：US17408152
申请日：2021-08-20
Applicant: Xilinx, Inc.
Inventor： Siva Santosh Kumar Pyla , Ravinder Sharma , Gokul Kavungal Nechikott , Saifuddin Kaijar , Brian S. Martin , Suraj Patel , Rishabh Gupta , Ch Vamshi Krishna , Kaustuv Manji
IPC: G06F9/445 , G06F9/4401 , G06F13/42
Abstract: Changing accelerator card images without rebooting a host system includes receiving, within an integrated circuit (IC) of an accelerator card, an address of a platform image stored in a non-volatile memory of the accelerator card. The address is received over a communication link between the host system and the accelerator card while the communication link is connected. Changing accelerator card images includes detecting, within a register of the IC, that a warm boot enable flag is set and that the communication link with the host system is disconnected. In response to detecting that the warm boot enable flag is set and that the communication link is disconnected, loading of the platform image from the address of the non-volatile memory into the integrated circuit is initiated.
-
公开(公告)号：US11443018B2
公开(公告)日：2022-09-13
申请号：US16299575
申请日：2019-03-12
Applicant: Xilinx, Inc.
Inventor： Brian S. Martin , Premduth Vidyanandan , Mark B. Carson , Neil Watson , Gary J. McClintock
Abstract: An example hardware accelerator for a computer system includes a programmable device and further includes kernel logic configured in a programmable fabric of the programmable device, and an intellectual property (IP) checker circuit in the kernel logic. The IP checker circuit is configured to obtain a device identifier (ID) of the programmable device and a signed whitelist, the signed whitelist including a list of device IDs and a signature, verify the signature of the signed whitelist, compare the device ID against the list of device IDs, and selectively assert or deassert an enable of the kernel logic in response to presence or absence, respectively, of the device ID in the list of device IDs and verification of the signature.
-
-
-
-
-
-
-
-
-
Search Results
11
records
(took 0.012 seconds)
