公开(公告)号：US20140085003A1

公开(公告)日：2014-03-27

申请号：US13629123

申请日：2012-09-27

Applicant: Xilinx, Inc.

Inventor： Patrick J. Quinn ,  John K. Jennings ,  Darragh Walsh ,  Padraig Kelly

IPC: H03F3/45 ,  H05K13/00

CPC classification number: H03F3/45 ,  H03F1/56 ,  Y10T29/49002

Abstract: A circuit includes an amplifier including a differential input stage including a first input terminal and a second input terminal. The circuit further includes a differential input line coupled to the first input terminal and the second input terminal, and shielding at least partially encompassing the differential input line. The shielding is connected to a node of the differential input stage of the amplifier.

Abstract translation: 电路包括放大器，其包括具有第一输入端和第二输入端的差分输入级。 电路还包括耦合到第一输入端和第二输入端的差分输入线，以及至少部分地包围差分输入线的屏蔽。 屏蔽连接到放大器差分输入级的一个节点。

公开(公告)号：US08902004B2

公开(公告)日：2014-12-02

申请号：US13629123

申请日：2012-09-27

Applicant: Xilinx, Inc.

Inventor： Patrick J. Quinn ,  John K. Jennings ,  Darragh Walsh ,  Padraig Kelly

IPC: H03F3/45

CPC classification number: H03F3/45 ,  H03F1/56 ,  Y10T29/49002

Abstract: A circuit includes an amplifier including a differential input stage including a first input terminal and a second input terminal. The circuit further includes a differential input line coupled to the first input terminal and the second input terminal, and shielding at least partially encompassing the differential input line. The shielding is connected to a node of the differential input stage of the amplifier.

Abstract translation: 电路包括放大器，其包括具有第一输入端和第二输入端的差分输入级。 电路还包括耦合到第一输入端和第二输入端的差分输入线，以及至少部分地包围差分输入线的屏蔽。 屏蔽连接到放大器差分输入级的一个节点。

公开(公告)号：US10545053B2

公开(公告)日：2020-01-28

申请号：US15616765

申请日：2017-06-07

Applicant: Xilinx, Inc.

Inventor： Umanath R. Kamath ,  Padraig Kelly ,  John K. Jennings

IPC: G01K7/00 ,  G01K7/01 ,  H03K19/003 ,  H03K19/0175 ,  G01K1/02

Abstract: An example dynamic element matching (DEM) circuit includes: a plurality of bipolar junction transistors (BJTs), each of the plurality of BJTs having a base terminal and a collector terminal coupled to electrical ground; a plurality of pairs of force switches, each pair of force switches coupled to an emitter of a respective one of the plurality of BJTs; a plurality of pairs of sense switches, where each pair of sense switches is coupled to the emitter of a respective one of the plurality of BJTs, a first switch in each pair of sense switches is coupled to a first node, and a second switch in each pair of sense switches is coupled to a second node; a first current source coupled to a first switch in each pair of force switches; and a second current source coupled to a second switch in each pair of force switches.

公开(公告)号：US20180356294A1

公开(公告)日：2018-12-13

申请号：US15616765

申请日：2017-06-07

Applicant: Xilinx, Inc.

Inventor： Umanath R. Kamath ,  Padraig Kelly ,  John K. Jennings

IPC: G01K7/01 ,  H03K19/003 ,  H03K19/0175

CPC classification number: G01K7/01 ,  G01K1/026 ,  G01K7/015 ,  H03K19/00307 ,  H03K19/017581

Abstract: An example dynamic element matching (DEM) circuit includes: a plurality of bipolar junction transistors (BJTs), each of the plurality of BJTs having a base terminal and a collector terminal coupled to electrical ground; a plurality of pairs of force switches, each pair of force switches coupled to an emitter of a respective one of the plurality of BJTs; a plurality of pairs of sense switches, where each pair of sense switches is coupled to the emitter of a respective one of the plurality of BJTs, a first switch in each pair of sense switches is coupled to a first node, and a second switch in each pair of sense switches is coupled to a second node; a first current source coupled to a first switch in each pair of force switches; and a second current source coupled to a second switch in each pair of force switches.