-
公开(公告)号：US20150002326A1
公开(公告)日：2015-01-01
申请号：US13928798
申请日：2013-06-27
Applicant: Xilinx, Inc.
Inventor： Brendan Farley , James Hudner , Ivan Bogue , Declan Carey , Darragh Walsh , Marc Erett
IPC: H03M1/12
Abstract: An analog-to-digital converter (“ADC”) is disclosed. The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.
Abstract translation: 公开了一种模拟 - 数字转换器（“ADC”）。 ADC包括一组比较器和一个窗口控制器。 窗口控制器耦合到比较器组，以选择性地激活与窗口大小相关联的比较器组的第一比较器，并且选择性地使比较器组的第二比较器失活。
-
2.发明申请公开(公告)号：US20140085003A1
公开(公告)日：2014-03-27
申请号：US13629123
申请日：2012-09-27
Applicant: Xilinx, Inc.
Inventor： Patrick J. Quinn , John K. Jennings , Darragh Walsh , Padraig Kelly
CPC classification number: H03F3/45 , H03F1/56 , Y10T29/49002
Abstract: A circuit includes an amplifier including a differential input stage including a first input terminal and a second input terminal. The circuit further includes a differential input line coupled to the first input terminal and the second input terminal, and shielding at least partially encompassing the differential input line. The shielding is connected to a node of the differential input stage of the amplifier.
Abstract translation: 电路包括放大器，其包括具有第一输入端和第二输入端的差分输入级。 电路还包括耦合到第一输入端和第二输入端的差分输入线，以及至少部分地包围差分输入线的屏蔽。 屏蔽连接到放大器差分输入级的一个节点。
-
Patent Agency Ranking
3.发明授权公开(公告)号：US10290330B1
公开(公告)日：2019-05-14
申请号：US15832515
申请日：2017-12-05
Applicant: Xilinx, Inc.
Inventor： Umanath R. Kamath , John K. Jennings , Edward Cullen , Ionut C. Cical , Darragh Walsh
Abstract: An example voltage reference circuit includes: a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate a complementary-to-temperature current and corresponding second control voltage; a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the complementary-to-temperature current.
-
公开(公告)号：US10404265B1
公开(公告)日：2019-09-03
申请号：US16117650
申请日：2018-08-30
Applicant: Xilinx, Inc.
Inventor： Brendan Farley , Bruno Miguel Vaz , Darragh Walsh
Abstract: An example apparatus includes a first transistor coupled between a supply node and a first node, a current mirror having a first side and a second side, and a second transistor coupled between the first node and the first side of the current mirror. The input buffer further includes a third transistor coupled between the first node and the second side of the current mirror, and a first capacitor coupled between a source and a drain of the second transistor.
-
5.发明申请公开(公告)号：US20190172504A1
公开(公告)日：2019-06-06
申请号：US15832515
申请日：2017-12-05
Applicant: Xilinx, Inc.
Inventor： Umanath R. Kamath , John K. Jennings , Edward Cullen , Ionut C. Cical , Darragh Walsh
Abstract: An example voltage reference circuit includes: a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate a complementary-to-temperature current and corresponding second control voltage; a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the complementary-to-temperature current.
-
公开(公告)号：US08970419B2
公开(公告)日：2015-03-03
申请号：US13928798
申请日：2013-06-27
Applicant: Xilinx, Inc.
Inventor： Brendan Farley , James Hudner , Ivan Bogue , Declan Carey , Darragh Walsh , Marc Erett
Abstract: An analog-to-digital converter (“ADC”). The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.
Abstract translation: 一个模拟 - 数字转换器（“ADC”）。 ADC包括一组比较器和一个窗口控制器。 窗口控制器耦合到比较器组，以选择性地激活与窗口大小相关联的比较器组的第一比较器，并且选择性地使比较器组的第二比较器失活。
-
公开(公告)号：US08902004B2
公开(公告)日：2014-12-02
申请号：US13629123
申请日：2012-09-27
Applicant: Xilinx, Inc.
Inventor： Patrick J. Quinn , John K. Jennings , Darragh Walsh , Padraig Kelly
IPC: H03F3/45
CPC classification number: H03F3/45 , H03F1/56 , Y10T29/49002
Abstract: A circuit includes an amplifier including a differential input stage including a first input terminal and a second input terminal. The circuit further includes a differential input line coupled to the first input terminal and the second input terminal, and shielding at least partially encompassing the differential input line. The shielding is connected to a node of the differential input stage of the amplifier.
Abstract translation: 电路包括放大器，其包括具有第一输入端和第二输入端的差分输入级。 电路还包括耦合到第一输入端和第二输入端的差分输入线，以及至少部分地包围差分输入线的屏蔽。 屏蔽连接到放大器差分输入级的一个节点。
-
-
-
-
-
-
Search Results
7
records
(took 0.015 seconds)
