公开(公告)号：US09453870B1

公开(公告)日：2016-09-27

申请号：US14252958

申请日：2014-04-15

Applicant: Xilinx, Inc.

Inventor： Amitava Majumdar ,  Richard W. Swanson ,  Anna W. Wong ,  Suraj Ethirajan ,  Asim A. Bajwa ,  Jongheon Jeong

IPC: G01R31/14 ,  G01R31/02

CPC classification number: G01R31/021 ,  G01R19/2513 ,  G01R31/025 ,  G01R31/2853

Abstract: In an apparatus relating generally to an IC die, the IC die has a regulated power supply, a power supply grid, and a test circuit. The regulated power supply is biased between a source supply node and a source ground node, which are externally accessible nodes of the IC die. An internal supply node of the power supply grid is coupled to the regulated power supply. The test circuit is coupled to the internal supply node of the power supply grid. The test circuit is configured to test for at least one short in the power supply grid. The test circuit is configured to limit power through the power supply grid to less than that of a probe tip tolerance. The test circuit is configured to test for the at least one short in presence of background current leakage of the power supply grid.

Abstract translation: 在与IC芯片大致相关的装置中，IC芯片具有稳压电源，电源网格和测试电路。 稳压电源在源电源节点和源极接地节点之间偏置，源极接地节点是IC芯片的外部可访问节点。 电源网格的内部供电节点耦合到稳压电源。 测试电路耦合到电源网格的内部供电节点。 测试电路被配置为测试电源网格中的至少一个短路。 测试电路被配置为将电源网格的电力限制为小于探针尖端公差的电力。 测试电路被配置为在存在电源网格的背景电流泄漏的情况下测试至少一个短路。