公开(公告)号：US09012245B1

公开(公告)日：2015-04-21

申请号：US14493078

申请日：2014-09-22

Applicant: Xilinx, Inc.

Inventor： Matthew H. Klein ,  Robert W. Wells ,  Jongheon Jeong

IPC: H01L21/44 ,  H01L21/66

CPC classification number: H01L22/20 ,  H01L22/14 ,  H01L22/22 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/15311

Abstract: In the disclosed methods, integrated circuit (IC) dice are manufactured from a common specification, and the IC dice are tested for defective circuitry. Respective defect sets are generated to indicate defective circuitry in the IC die. The dice are assigned to bins based on the respective defect sets. For each bin, all IC dice assigned to the bin have equivalent respective defect sets. Product definitions are provided, and each product definition indicates a respective set of circuitry required for a corresponding product. Respective sets of packages are manufactured for each product. In the manufacturing of each package of a respective set of packages for each product, one or more IC dice are selected from a subset of the plurality of bins such that the IC dice have respective defect sets allowed by the product definition of the product. The selected IC dice are then manufactured into the package.

Abstract translation: 在所公开的方法中，集成电路（IC）芯片由公共规范制造，IC芯片被测试有缺陷的电路。 产生各个缺陷组以指示IC芯片中的有缺陷的电路。 基于相应的缺陷集，将骰子分配给箱子。 对于每个仓，分配给仓的所有IC骰子都具有相应的各自的缺陷集。 提供了产品定义，每个产品定义都表示相应产品所需的相应电路组。 为每个产品制造各套包装。 在针对每个产品的相应的一组包装的每个包装的制造中，从多个箱的子集中选择一个或多个IC骰子，使得IC骰子具有由产品的产品定义允许的各自的缺陷组。 然后将选定的IC芯片制造成封装。

公开(公告)号：US09453870B1

公开(公告)日：2016-09-27

申请号：US14252958

申请日：2014-04-15

Applicant: Xilinx, Inc.

Inventor： Amitava Majumdar ,  Richard W. Swanson ,  Anna W. Wong ,  Suraj Ethirajan ,  Asim A. Bajwa ,  Jongheon Jeong

IPC: G01R31/14 ,  G01R31/02

CPC classification number: G01R31/021 ,  G01R19/2513 ,  G01R31/025 ,  G01R31/2853

Abstract: In an apparatus relating generally to an IC die, the IC die has a regulated power supply, a power supply grid, and a test circuit. The regulated power supply is biased between a source supply node and a source ground node, which are externally accessible nodes of the IC die. An internal supply node of the power supply grid is coupled to the regulated power supply. The test circuit is coupled to the internal supply node of the power supply grid. The test circuit is configured to test for at least one short in the power supply grid. The test circuit is configured to limit power through the power supply grid to less than that of a probe tip tolerance. The test circuit is configured to test for the at least one short in presence of background current leakage of the power supply grid.

Abstract translation: 在与IC芯片大致相关的装置中，IC芯片具有稳压电源，电源网格和测试电路。 稳压电源在源电源节点和源极接地节点之间偏置，源极接地节点是IC芯片的外部可访问节点。 电源网格的内部供电节点耦合到稳压电源。 测试电路耦合到电源网格的内部供电节点。 测试电路被配置为测试电源网格中的至少一个短路。 测试电路被配置为将电源网格的电力限制为小于探针尖端公差的电力。 测试电路被配置为在存在电源网格的背景电流泄漏的情况下测试至少一个短路。