公开(公告)号：US09842187B1

公开(公告)日：2017-12-12

申请号：US15082993

申请日：2016-03-28

Applicant: Xilinx, Inc.

Inventor： Jindrich Zejda ,  Atul Srinivasan ,  Ilya K. Ganusov ,  Walter A. Manaker, Jr. ,  Benjamin S. Devlin ,  Satish B. Sivaswamy

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5054 ,  G06F2217/84

Abstract: Approaches for processing a circuit design include determining pin slack values for pins of the circuit elements in the circuit design. A processor selects a subset of endpoints based on pin slack values of the endpoints being in a critical slack range and determines startpoints of the circuit design that are in respective critical fanin cones. For each endpoint of the subset, the processor determines an arrival time from each startpoint in the respective critical fanin cone and determines for each startpoint-endpoint pair, a respective set of constraint values as a function of the respective arrival time from the startpoint. The processor generates a graph in the memory circuit from the startpoint-endpoint pairs. First nodes in the graph represent the startpoints and second nodes in the graph represent the endpoints, and values in the respective set of constraint values are associated with edges that connect the nodes.