公开(公告)号：US10289093B1

公开(公告)日：2019-05-14

申请号：US15850659

申请日：2017-12-21

Applicant: Xilinx, Inc.

Inventor： Patrick Lysaght ,  Parimal Patel ,  Yun Qu ,  Graham F. Schelle

IPC: G06F7/38 ,  H03K19/173 ,  G05B19/045 ,  G05B19/042

Abstract: A system can include a finite state machine generator implemented in programmable circuitry of an integrated circuit. The finite state machine generator is parameterizable to implement different finite state machines at runtime of the integrated circuit. The system can include a processor configured to execute program code. The processor is configured to provide first parameterization data to the finite state machine generator at runtime of the integrated circuit. The first parameterization data specifies a first finite state machine and the finite state machine generator implements the first finite state machine in response to receiving the first parameterization data from the processor.

公开(公告)号：US10474610B1

公开(公告)日：2019-11-12

申请号：US15676530

申请日：2017-08-14

Applicant: Xilinx, Inc.

Inventor： Graham F. Schelle ,  Patrick Lysaght ,  Yun Qu ,  Parimal Patel

IPC: G06F11/00 ,  G06F13/40 ,  G06F15/78 ,  G06F13/28 ,  G06F11/34 ,  G06F11/36

Abstract: An integrated circuit can include programmable circuitry configured to implement an overlay circuit specified by an overlay. The overlay circuit can include a trace buffer configured to receive a probed signal from circuitry within the overlay circuit. The trace buffer can be configured to generate trace data from the probed signal and store the trace data in a runtime allocated memory. The integrated circuit also can include a processor coupled to the programmable circuitry and configured to control operation of the trace buffer. The processor can be configured to read the trace data from the runtime allocated memory.