公开(公告)号：US20140245040A1

公开(公告)日：2014-08-28

申请号：US13780834

申请日：2013-02-28

申请人： Yair Baram ,  Hanan Borukhov ,  Idan Alrod ,  Eran Sharon

发明人： Yair Baram ,  Hanan Borukhov ,  Idan Alrod ,  Eran Sharon

IPC分类号： G06F1/32

CPC分类号： G06F1/3275 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3246 ,  Y02D10/13 ,  Y02D10/14

摘要： The present application is directed to systems and methods for managing data in a system for hibernation states. In one implementation, a memory device comprises a controller memory, a main memory, a buffer to the main memory and a controller comprising a processor. The processor is configured to manage data storage in conjunction with hibernation of the memory device. The processor is in communication with the controller memory, the main memory and the buffer, and is configured to read data from the controller memory; write at least a portion of the data read from the controller memory into the buffer prior to the memory device entering a hibernation state; and after writing the at least a portion of the data read from the controller memory into the buffer and prior to the memory device entering the hibernation state, reduce an amount of power provided to the buffer of the to a reduced power level.

摘要翻译： 本申请涉及用于管理用于休眠状态的系统中的数据的系统和方法。 在一个实现中，存储器件包括控制器存储器，主存储器，到主存储器的缓冲器和包括处理器的控制器。 处理器被配置为结合存储器设备的休眠来管理数据存储。 处理器与控制器存储器，主存储器和缓冲器通信，并被配置为从控制器存储器读取数据; 在存储器件进入休眠状态之前将从控制器存储器读取的数据的至少一部分写入缓冲器; 并且在将从控制器存储器读取的数据的至少一部分写入缓冲器之后并且在存储器件进入休眠状态之前，将提供给缓冲器的功率量减少到降低的功率电平。

公开(公告)号：US09239610B2

公开(公告)日：2016-01-19

申请号：US13780834

申请日：2013-02-28

申请人： Yair Baram ,  Hanan Borukhov ,  Idan Alrod ,  Eran Sharon

发明人： Yair Baram ,  Hanan Borukhov ,  Idan Alrod ,  Eran Sharon

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3275 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3246 ,  Y02D10/13 ,  Y02D10/14

摘要： The present application is directed to systems and methods for managing data in a system for hibernation states. In one implementation, a memory device comprises a controller memory, a main memory, a buffer to the main memory and a controller comprising a processor. The processor is configured to manage data storage in conjunction with hibernation of the memory device. The processor is in communication with the controller memory, the main memory and the buffer, and is configured to read data from the controller memory; write at least a portion of the data read from the controller memory into the buffer prior to the memory device entering a hibernation state; and after writing the at least a portion of the data read from the controller memory into the buffer and prior to the memory device entering the hibernation state, reduce an amount of power provided to the buffer of the to a reduced power level.

摘要翻译： 本申请涉及用于管理用于休眠状态的系统中的数据的系统和方法。 在一个实现中，存储器件包括控制器存储器，主存储器，到主存储器的缓冲器和包括处理器的控制器。 处理器被配置为结合存储器设备的休眠来管理数据存储。 处理器与控制器存储器，主存储器和缓冲器通信，并被配置为从控制器存储器读取数据; 在存储器件进入休眠状态之前将从控制器存储器读取的数据的至少一部分写入缓冲器; 并且在将从控制器存储器读取的数据的至少一部分写入缓冲器之后并且在存储器件进入休眠状态之前，将提供给缓冲器的功率量减少到降低的功率电平。