公开(公告)号：US07577037B2

公开(公告)日：2009-08-18

申请号：US11619513

申请日：2007-01-03

申请人： Yan Li ,  Emilio Yero

发明人： Yan Li ,  Emilio Yero

IPC分类号： G11C16/06

CPC分类号： G11C16/26 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G11C7/22 ,  G11C16/04 ,  G11C2207/2245 ,  Y02D10/13

摘要： Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.

摘要翻译： 存在用于通过允许具有相同存储器的操作的相间流水线来提高非易失性存储器件中的性能的方法和电路，从而允许在写入操作的脉冲和验证阶段之间交错读取操作。 在示例性实施例中，两个操作共享数据锁存器。 在具体示例中，在多级写入操作中的验证所需的数据锁存器中，它们可用于存储在多级写入中的步骤之间执行的读取期间从另一位置读取的数据。 在示例性实施例中，多级写入仅需要暂停，执行读取，并在暂停点恢复写入。

公开(公告)号：US20070109867A1

公开(公告)日：2007-05-17

申请号：US11619513

申请日：2007-01-03

申请人： Yan Li ,  Emilio Yero

发明人： Yan Li ,  Emilio Yero

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G11C7/22 ,  G11C16/04 ,  G11C2207/2245 ,  Y02D10/13

摘要： Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.

摘要翻译： 存在用于通过允许具有相同存储器的操作的相间流水线来提高非易失性存储器件中的性能的方法和电路，从而允许在写入操作的脉冲和验证阶段之间交错读取操作。 在示例性实施例中，两个操作共享数据锁存器。 在具体示例中，在多级写入操作中的验证所需的数据锁存器中，它们可用于存储在多级写入中的步骤之间执行的读取期间从另一位置读取的数据。 在示例性实施例中，多级写入仅需要暂停，执行读取，并在暂停点恢复写入。

公开(公告)号：US07936602B2

公开(公告)日：2011-05-03

申请号：US12495200

申请日：2009-06-30

申请人： Yan Li ,  Emilio Yero

发明人： Yan Li ,  Emilio Yero

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G11C7/22 ,  G11C16/04 ,  G11C2207/2245 ,  Y02D10/13

摘要： Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.

摘要翻译： 存在用于通过允许具有相同存储器的操作的相间流水线来提高非易失性存储器件中的性能的方法和电路，从而允许在写入操作的脉冲和验证阶段之间交错读取操作。 在示例性实施例中，两个操作共享数据锁存器。 在具体示例中，在多级写入操作中的验证所需的数据锁存器中，它们可用于存储在多级写入中的步骤之间执行的读取期间从另一位置读取的数据。 在示例性实施例中，多级写入仅需要暂停，执行读取，并在暂停点恢复写入。

公开(公告)号：US20090262578A1

公开(公告)日：2009-10-22

申请号：US12495200

申请日：2009-06-30

申请人： Yan Li ,  Emilio Yero

发明人： Yan Li ,  Emilio Yero

IPC分类号： G11C16/04 ,  G11C7/10 ,  G11C16/06

CPC分类号： G11C16/26 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G11C7/22 ,  G11C16/04 ,  G11C2207/2245 ,  Y02D10/13

摘要： Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.

摘要翻译： 存在用于通过允许具有相同存储器的操作的相间流水线来提高非易失性存储器件中的性能的方法和电路，从而允许在写入操作的脉冲和验证阶段之间交错读取操作。 在示例性实施例中，两个操作共享数据锁存器。 在具体示例中，在多级写入操作中的验证所需的数据锁存器中，它们可用于存储在多级写入中的步骤之间执行的读取期间从另一位置读取的数据。 在示例性实施例中，多级写入仅需要暂停，执行读取，并在暂停点恢复写入。

公开(公告)号：US07206230B2

公开(公告)日：2007-04-17

申请号：US11097590

申请日：2005-04-01

申请人： Yan Li ,  Emilio Yero

发明人： Yan Li ,  Emilio Yero

IPC分类号： G11C11/34 ,  G11C16/06 ,  G11C7/10 ,  G11C16/04

CPC分类号： G11C16/26 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G11C7/22 ,  G11C16/04 ,  G11C2207/2245 ,  Y02D10/13

摘要： Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.

摘要翻译： 存在用于通过允许具有相同存储器的操作的相间流水线来提高非易失性存储器件中的性能的方法和电路，从而允许在写入操作的脉冲和验证阶段之间交错读取操作。 在示例性实施例中，两个操作共享数据锁存器。 在具体示例中，在多级写入操作中的验证所需的数据锁存器中，它们可用于存储在多级写入中的步骤之间执行的读取期间从另一位置读取的数据。 在示例性实施例中，多级写入仅需要暂停，执行读取，并在暂停点恢复写入。

公开(公告)号：US20060221704A1

公开(公告)日：2006-10-05

申请号：US11097590

申请日：2005-04-01

申请人： Yan Li ,  Emilio Yero

发明人： Yan Li ,  Emilio Yero

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G11C7/22 ,  G11C16/04 ,  G11C2207/2245 ,  Y02D10/13

摘要： Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.

公开(公告)号：USD965092S1

公开(公告)日：2022-09-27

申请号：US29802936

申请日：2021-08-09

申请人： Yan Li ,  Weijian Yuan

设计人： Yan Li ,  Weijian Yuan

公开(公告)号：USD948651S1

公开(公告)日：2022-04-12

申请号：US29782448

申请日：2021-05-06

申请人： Yan Li

设计人： Yan Li

公开(公告)号：US09436885B2

公开(公告)日：2016-09-06

申请号：US13558969

申请日：2012-07-26

申请人： Yan Li ,  Hai Bo Lin ,  Tao Liu ,  Yu Dong Yang ,  Yi Xin Zhao

发明人： Yan Li ,  Hai Bo Lin ,  Tao Liu ,  Yu Dong Yang ,  Yi Xin Zhao

IPC分类号： H04N7/18 ,  G06K9/32 ,  G06K9/26

CPC分类号： G06K1/121 ,  G06K7/1439 ,  G06K9/26 ,  G06K9/3233 ,  H05K7/18

摘要： A system and method for accurately positioning a computer position, and identifying the specific rack position where the computer is without manual intervention. A camera is installed on the computer to read the contents of a tag on the rack, so as to identify the position information of the computer. Specifically, the computer is provided with a self-positioning function, wherein: a camera is installed on the computer, and the camera is configured to read the contents of a tag attached on a side of a rack to house the computer to identify the rack position where the computer is.

摘要翻译： 一种用于精确定位计算机位置的系统和方法，以及识别计算机没有手动干预的特定机架位置。 计算机上安装了相机以读取机架上标签的内容，以便识别计算机的位置信息。 具体地说，该计算机具有自定位功能，其中：相机安装在计算机上，并且相机被配置为读取安装在机架一侧的标签的内容以容纳计算机以识别机架 电脑的位置

公开(公告)号：US09213197B2

公开(公告)日：2015-12-15

申请号：US13703719

申请日：2012-07-13

申请人： Qiangtao Wang ,  Wenbing Li ,  Xinli Ma ,  Yan Li

发明人： Qiangtao Wang ,  Wenbing Li ,  Xinli Ma ,  Yan Li

IPC分类号： G02F1/1335 ,  G02B5/20

CPC分类号： G02F1/133514 ,  G02B5/201 ,  G02B2207/113 ,  G02F2201/52

摘要： Embodiments of the present invention provide a color filter substrate, a liquid crystal panel and a liquid crystal display. The color filter substrate comprises a plurality of elementary pixels. Each of the elementary pixels comprises sub-pixels in four colors. Among the sub-pixels in four colors, a sub-pixel in at least one of the colors has a number larger than or equal to 2.

摘要翻译： 本发明的实施例提供一种滤色器基板，液晶面板和液晶显示器。 滤色器基板包括多个基本像素。 每个基本像素包括四种颜色的子像素。 在四种颜色的子像素中，至少一种颜色的子像素的数目大于或等于2。