公开(公告)号：US07324386B2

公开(公告)日：2008-01-29

申请号：US11308668

申请日：2006-04-20

Applicant: Yang-Chieh Lin

Inventor： Yang-Chieh Lin

IPC: G11C16/04

CPC classification number: G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445

Abstract: A method for erasing a flash memory group is provided, which comprises the following steps. (a) Apply a erase (ERS) pulse to a first subset of the group. (b) Perform one of a soft program verification (SPGMV) and a tight soft program verification (TSPGMV) on the first subset of the group. (c) Repeat steps (a) and (b) until a first predetermined condition is true. (d) Perform an erase verification (ERSV) on a second subset of the group. (e) Repeat steps (a) to (d) until a second predetermined condition is true. And (f) fix bit line leakage in a third subset of the group with a slow program (SLPGM) and apply an ERS pulse to the third subset.

Abstract translation: 提供了一种擦除闪存组的方法，包括以下步骤。 （a）将擦除（ERS）脉冲应用于组的第一个子集。 （b）在组的第一个子集上执行软程序验证（SPGMV）和严格的软程序验证（TSPGMV）之一。 （c）重复步骤（a）和（b），直到第一个预定条件为真。 （d）在组的第二个子集上执行擦除验证（ERSV）。 （e）重复步骤（a）至（d），直到第二个预定条件为真。 和（f）用慢程序（SLPGM）修复组的第三个子集中的位线泄漏，并将ERS脉冲应用于第三个子集。

公开(公告)号：US20120230119A1

公开(公告)日：2012-09-13

申请号：US13477431

申请日：2012-05-22

Applicant: Chung-Zen Chen ,  Yang-Chieh Lin ,  Chung-Shan Kuo

Inventor： Chung-Zen Chen ,  Yang-Chieh Lin ,  Chung-Shan Kuo

IPC: G11C16/10

CPC classification number: G11C16/14 ,  G11C16/02 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/16

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Abstract translation: 一种非易失性存储器件，包括存储器阵列，该存储器阵列具有被组织为扇区的多个存储器单元，每个扇区具有与多个本地字线相关联的主字线，每个本地字线通过 各自的本地字线驱动电路，每个本地字线驱动电路由耦合在相应主字线和相应本地字线之间的第一MOS晶体管和耦合在相应本地字线和第一 偏置端子

公开(公告)号：US08189396B2

公开(公告)日：2012-05-29

申请号：US11610573

申请日：2006-12-14

Applicant: Chung-Zen Chen ,  Yang-Chieh Lin ,  Chung-Shan Kuo

Inventor： Chung-Zen Chen ,  Yang-Chieh Lin ,  Chung-Shan Kuo

IPC: G11C16/08

CPC classification number: G11C16/14 ,  G11C16/02 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/16

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Abstract translation: 一种非易失性存储器件，包括存储器阵列，该存储器阵列具有被组织为扇区的多个存储器单元，每个扇区具有与多个本地字线相关联的主字线，每个本地字线通过 各自的本地字线驱动电路，每个本地字线驱动电路由耦合在相应主字线和相应本地字线之间的第一MOS晶体管和耦合在相应本地字线和第一 偏置端子

公开(公告)号：US20080036528A1

公开(公告)日：2008-02-14

申请号：US11463597

申请日：2006-08-10

Applicant: Chung-Zen Chen ,  Chung-Shan Kuo ,  Yang-Chieh Lin

Inventor： Chung-Zen Chen ,  Chung-Shan Kuo ,  Yang-Chieh Lin

IPC: G05F1/10

CPC classification number: H02M3/07

Abstract: A charge pump circuit including a plurality of controlled charge pumps (CPs), a plurality of uncontrolled CPs, a plurality of control units, and an output unit is provided. Each controlled CP determines whether to provide charges to a node by a control signal, and each uncontrolled CP constantly provides charges to the node. The higher the node voltage at the node is, the more the controlled CPs not providing charge to the node are, so as to suppress the voltage of the node. In addition, the output unit regulates and outputs an output voltage according to the node voltage by the negative feedback.

Abstract translation: 提供了包括多个受控电荷泵（CP），多个不受控制的CP，多个控制单元和输出单元的电荷泵电路。 每个受控CP确定是否通过控制信号向节点提供费用，并且每个不受控制的CP不断向节点提供费用。 节点处的节点电压越高，对节点不提供电荷的受控CP越多，以抑制节点的电压。 此外，输出单元通过负反馈调节并输出根据节点电压的输出电压。

公开(公告)号：US20070247922A1

公开(公告)日：2007-10-25

申请号：US11308668

申请日：2006-04-20

Applicant: Yang-Chieh Lin

Inventor： Yang-Chieh Lin

IPC: G11C16/04 ,  G11C11/34 ,  G11C16/06

CPC classification number: G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445

Abstract: A method for erasing a flash memory group is provided, which comprises the following steps. (a) Apply a erase (ERS) pulse to a first subset of the group. (b) Perform one of a soft program verification (SPGMV) and a tight soft program verification (TSPGMV) on the first subset of the group. (c) Repeat steps (a) and (b) until a first predetermined condition is true. (d) Perform an erase verification (ERSV) on a second subset of the group. (e) Repeat steps (a) to (d) until a second predetermined condition is true. And (f) fix bit line leakage in a third subset of the group with a slow program (SLPGM) and apply an ERS pulse to the third subset.

Abstract translation: 提供了一种擦除闪存组的方法，包括以下步骤。 （a）将擦除（ERS）脉冲应用于组的第一个子集。 （b）在组的第一个子集上执行软程序验证（SPGMV）和严格的软程序验证（TSPGMV）之一。 （c）重复步骤（a）和（b），直到第一个预定条件为真。 （d）在组的第二个子集上执行擦除验证（ERSV）。 （e）重复步骤（a）至（d），直到第二个预定条件为真。 和（f）用慢程序（SLPGM）修复组的第三个子集中的位线泄漏，并将ERS脉冲应用于第三个子集。

公开(公告)号：US20080144389A1

公开(公告)日：2008-06-19

申请号：US11610573

申请日：2006-12-14

Applicant: Chung-Zen Chen ,  Yang-Chieh Lin ,  Chung-Shan Kuo

Inventor： Chung-Zen Chen ,  Yang-Chieh Lin ,  Chung-Shan Kuo

IPC: G11C16/10

CPC classification number: G11C16/14 ,  G11C16/02 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/16

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Abstract translation: 一种非易失性存储器件，包括存储器阵列，该存储器阵列具有被组织为扇区的多个存储器单元，每个扇区具有与多个本地字线相关联的主字线，每个本地字线通过 各自的本地字线驱动电路，每个本地字线驱动电路由耦合在相应主字线和相应本地字线之间的第一MOS晶体管和耦合在相应本地字线和第一 偏置端子

公开(公告)号：US07132879B2

公开(公告)日：2006-11-07

申请号：US10711916

申请日：2004-10-13

Applicant: Yin-Chang Chen ,  Yang-Chieh Lin

Inventor： Yin-Chang Chen ,  Yang-Chieh Lin

IPC: G05F3/02

CPC classification number: H02M3/073

Abstract: A boost circuit capable of boosting a reference voltage into an output voltage. The boost circuit includes a main transistor electrically connected to the output voltage, an auxiliary transistor electrically connected to the output voltage, a pre-charge circuit electrically connected to the main transistor and the auxiliary transistor for pre-charging the main transistor and the auxiliary transistor, and a voltage detector electrically connected to the auxiliary transistor and the reference voltage for controlling the auxiliary transistor according to the reference voltage.

Abstract translation: 能够将参考电压升压成输出电压的升压电路。 升压电路包括电连接到输出电压的主晶体管，电连接到输出电压的辅助晶体管，电连接到主晶体管的预充电电路和用于对主晶体管和辅助晶体管进行预充电的辅助晶体管 以及电连接到辅助晶体管的电压检测器和用于根据参考电压控制辅助晶体管的参考电压。

公开(公告)号：US08456922B2

公开(公告)日：2013-06-04

申请号：US13477431

申请日：2012-05-22

Applicant: Chung-Zen Chen ,  Yang-Chieh Lin ,  Chung-Shan Kuo

Inventor： Chung-Zen Chen ,  Yang-Chieh Lin ,  Chung-Shan Kuo

IPC: G11C16/16

CPC classification number: G11C16/14 ,  G11C16/02 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/16

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

公开(公告)号：US07443230B2

公开(公告)日：2008-10-28

申请号：US11463597

申请日：2006-08-10

Applicant: Chung-Zen Chen ,  Chung-Shan Kuo ,  Yang-Chieh Lin

Inventor： Chung-Zen Chen ,  Chung-Shan Kuo ,  Yang-Chieh Lin

IPC: G05F1/10

CPC classification number: H02M3/07

Abstract: A charge pump circuit including a plurality of controlled charge pumps (CPs), a plurality of uncontrolled CPs, a plurality of control units, and an output unit is provided. Each controlled CP determines whether to provide charges to a node by a control signal, and each uncontrolled CP constantly provides charges to the node. The higher the node voltage at the node is, the more the controlled CPs not providing charge to the node are, so as to suppress the voltage of the node. In addition, the output unit regulates and outputs an output voltage according to the node voltage by the negative feedback.

Abstract translation: 提供了包括多个受控电荷泵（CP），多个不受控制的CP，多个控制单元和输出单元的电荷泵电路。 每个受控CP确定是否通过控制信号向节点提供费用，并且每个不受控制的CP不断向节点提供费用。 节点处的节点电压越高，对节点不提供电荷的受控CP越多，以抑制节点的电压。 此外，输出单元通过负反馈调节并输出根据节点电压的输出电压。

公开(公告)号：US07382661B1

公开(公告)日：2008-06-03

申请号：US11672406

申请日：2007-02-07

Applicant: Yang-Chieh Lin

Inventor： Yang-Chieh Lin

IPC: G11C16/00

CPC classification number: G11C16/10

Abstract: A program method for a flash memory semiconductor device includes the steps of providing a bit line voltage for programming a group of memory cells and detecting if the bit line voltage meets a selected target voltage. When the bit line voltage meets the selected target voltage, a program operation is performed on the group of memory cells. When the bit line voltage does not meet the selected target voltage, the programming operation is individually performed on at least a first subgroup of memory cells from the group and a second subgroup of memory cells from the group.

Abstract translation: 一种用于闪速存储器半导体器件的程序方法，包括以下步骤：提供用于对一组存储器单元进行编程的位线电压，以及检测位线电压是否满足所选择的目标电压。 当位线电压满足所选择的目标电压时，对存储器单元组执行编程操作。 当位线电压不满足所选择的目标电压时，对组中的至少第一组存储器单元和来自组的存储器单元的第二子组分别进行编程操作。