公开(公告)号：US08004890B2

公开(公告)日：2011-08-23

申请号：US12437826

申请日：2009-05-08

申请人： Yao-Wen Chang ,  Tao-Cheng Lu ,  I-Chen Yang ,  Hsing-Wen Chang

发明人： Yao-Wen Chang ,  Tao-Cheng Lu ,  I-Chen Yang ,  Hsing-Wen Chang

IPC分类号： G11C11/34

CPC分类号： G11C16/0475 ,  G11C11/56 ,  G11C16/3418 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5634

摘要： An operation method of a non-volatile memory for reducing the second-bit effect in the non-volatile memory is suitable for an N-level memory cell having a first storage position and a second storage position (wherein N is a positive integer greater than 2). The method includes following steps: determining sets of operation levels for operating the first storage position according to the level of the second storage position; when the level of the second storage position is a lower level, operating the first storage position according to a first set of operation levels; when the level of the second storage position is a higher level, operating the first storage position according to a second set of operation levels. Each of the levels in the second set of operation levels is greater than the corresponding level in the first set of operation levels.

摘要翻译： 用于降低非易失性存储器中的第二位效应的非易失性存储器的操作方法适合于具有第一存储位置和第二存储位置的N级存储器单元（其中N是大于 2）。 该方法包括以下步骤：根据第二存储位置的水平确定用于操作第一存储位置的操作级别集合; 当第二存储位置的电平为较低电平时，根据第一组操作电平操作第一存储位置; 当第二存储位置的电平为较高电平时，根据第二组操作电平来操作第一存储位置。 第二组操作级别中的每个级别都大于第一组操作级别中的相应级别。

公开(公告)号：US20100284220A1

公开(公告)日：2010-11-11

申请号：US12437826

申请日：2009-05-08

申请人： Yao-Wen Chang ,  Tao-Cheng Lu ,  I-Chen Yang ,  Hsing-Wen Chang

发明人： Yao-Wen Chang ,  Tao-Cheng Lu ,  I-Chen Yang ,  Hsing-Wen Chang

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0475 ,  G11C11/56 ,  G11C16/3418 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5634

摘要： An operation method of a non-volatile memory for reducing the second-bit effect in the non-volatile memory is suitable for an N-level memory cell having a first storage position and a second storage position (wherein N is a positive integer greater than 2). The method includes following steps: determining sets of operation levels for operating the first storage position according to the level of the second storage position; when the level of the second storage position is a lower level, operating the first storage position according to a first set of operation levels; when the level of the second storage position is a higher level, operating the first storage position according to a second set of operation levels. Each of the levels in the second set of operation levels is greater than the corresponding level in the first set of operation levels.

摘要翻译： 用于降低非易失性存储器中的第二位效应的非易失性存储器的操作方法适用于具有第一存储位置和第二存储位置的N级存储器单元（其中N是大于 2）。 该方法包括以下步骤：根据第二存储位置的水平确定用于操作第一存储位置的操作级别集合; 当第二存储位置的电平为较低电平时，根据第一组操作电平操作第一存储位置; 当第二存储位置的电平为较高电平时，根据第二组操作电平来操作第一存储位置。 第二组操作级别中的每个级别都大于第一组操作级别中的相应级别。

公开(公告)号：US07486086B2

公开(公告)日：2009-02-03

申请号：US11979576

申请日：2007-11-06

申请人： Yao-Wen Chang ,  Hsing-Wen Chang ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Hsing-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G01R27/26

CPC分类号： G01R31/2621

摘要： A method for measuring intrinsic capacitance of a MOS device is provided. The MOS device includes a first terminal, a second terminal, a third terminal and a fourth terminal. First, provide a first input signal to the second terminal and ground the third terminal and fourth terminal. Then, charge the first terminal and measure a first current required for charging the first terminal. Afterward, provide a second input signal to the second terminal, ground the third terminal and the fourth terminal, and measure a second current required for charging the first terminal, wherein the first input signal and the second input signal have the same low level, but different high levels. Finally, determine intrinsic capacitance between the first terminal and the second terminal according to the first current, the second current and a high level difference between the first input signal and the second input signal.

摘要翻译： 提供了一种用于测量MOS器件的本征电容的方法。 MOS器件包括第一端子，第二端子，第三端子和第四端子。 首先，向第二终端提供第一输入信号，并将第三终端和第四终端接地。 然后，对第一终端充电并测量对第一终端充电所需的第一电流。 然后，向第二终端提供第二输入信号，将第三端子和第四端子接地，并测量对第一端子充电所需的第二电流，其中第一输入信号和第二输入信号具有相同的低电平，但是 不同的高层次。 最后，根据第一电流，第二电流和第一输入信号与第二输入信号之间的高电平差来确定第一端子和第二端子之间的本征电容。

公开(公告)号：US20080106274A1

公开(公告)日：2008-05-08

申请号：US11979576

申请日：2007-11-06

申请人： Yao-Wen Chang ,  Hsing-Wen Chang ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Hsing-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G01R27/26

CPC分类号： G01R31/2621

摘要： A method for measuring intrinsic capacitance of a MOS device is provided. The MOS device includes a first terminal, a second terminal, a third terminal and a fourth terminal. First, provide a first input signal to the second terminal and ground the third terminal and fourth terminal. Then, charge the first terminal and measure a first current required for charging the first terminal. Afterward, provide a second input signal to the second terminal, ground the third terminal and the fourth terminal, and measure a second current required for charging the first terminal, wherein the first input signal and the second input signal have the same low level, but different high levels. Finally, determine intrinsic capacitance between the first terminal and the second terminal according to the first current, the second current and a high level difference between the first input signal and the second input signal.

摘要翻译： 提供了一种用于测量MOS器件的本征电容的方法。 MOS器件包括第一端子，第二端子，第三端子和第四端子。 首先，向第二终端提供第一输入信号，并将第三终端和第四终端接地。 然后，对第一终端充电并测量对第一终端充电所需的第一电流。 然后，向第二终端提供第二输入信号，将第三端子和第四端子接地，并测量对第一端子充电所需的第二电流，其中第一输入信号和第二输入信号具有相同的低电平，但是 不同的高层次。 最后，根据第一电流，第二电流和第一输入信号与第二输入信号之间的高电平差来确定第一端子和第二端子之间的本征电容。

公开(公告)号：US08952484B2

公开(公告)日：2015-02-10

申请号：US12949092

申请日：2010-11-18

申请人： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L21/70 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/762

CPC分类号： H01L29/792 ,  H01L21/76232

摘要： A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The gate structure includes a charge storage structure, a gate and spacers. The charge storage structure is disposed on the substrate. The gate is disposed on the charge storage structure. The spacers are disposed on the sidewalls of the gate and the charge storage structure. The first doped region and the second doped region are respectively disposed in the substrate at two sides of the charge storage structure and at least located under the spacers. The isolation structures are respectively disposed in the substrate at two sides of the gate structure.

摘要翻译： 提供了一种非易失性存储器及其制造方法。 非挥发性存储器包括衬底，栅极结构，第一掺杂区，第二掺杂区和一对隔离结构。 栅极结构设置在基板上。 栅极结构包括电荷存储结构，栅极和间隔物。 电荷存储结构设置在基板上。 栅极设置在电荷存储结构上。 间隔件设置在栅极和电荷存储结构的侧壁上。 第一掺杂区域和第二掺杂区域分别设置在电荷存储结构的两侧的基板中，并且至少位于间隔物之下。 隔离结构分别设置在栅极结构的两侧的基板中。

公开(公告)号：US20110182123A1

公开(公告)日：2011-07-28

申请号：US12834228

申请日：2010-07-12

申请人： GUAN-WEI WU ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： GUAN-WEI WU ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  H01L29/792 ,  H01L21/336 ,  H01L29/78 ,  G11C16/16

CPC分类号： H01L29/792 ,  G11C16/0475 ,  H01L29/4234 ,  H01L29/42352

摘要： A flash memory and a manufacturing method and an operating method thereof are provided. The flash memory includes a substrate, a charge-trapping structure, a first gate, a second gate, a third gate, a first doped region and a second doped region. The substrate has a protrusion portion. The charge-trapping structure is disposed over the substrate. The first gate and the second gate are disposed respectively over the charge-trapping structure at two sides of the protrusion portion. The top surfaces of the first gate and the second gate are lower than the top surface of the charge-trapping structure located on the top of the protrusion portion. The third gate is disposed over the charge-trapping structure located on the top of the protrusion portion. The first doped region and the second doped region are disposed respectively in the substrate at two sides of the protrusion portion.

摘要翻译： 提供闪速存储器及其制造方法及其操作方法。 闪速存储器包括衬底，电荷俘获结构，第一栅极，第二栅极，第三栅极，第一掺杂区域和第二掺杂区域。 基板具有突起部。 电荷捕获结构设置在衬底上。 第一栅极和第二栅极分别设置在突出部分的两侧的电荷捕获结构的上方。 第一栅极和第二栅极的顶表面比位于突起部分顶部的电荷捕获结构的顶表面低。 第三栅极设置在位于突起部分的顶部上的电荷捕获结构之上。 第一掺杂区域和第二掺杂区域分别设置在基板的突出部分的两侧。

公开(公告)号：US20100302855A1

公开(公告)日：2010-12-02

申请号：US12614647

申请日：2009-11-09

申请人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu ,  Guan-Wei Wu ,  Tao-Yuan Lin ,  Po-Chou Chen

发明人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu ,  Guan-Wei Wu ,  Tao-Yuan Lin ,  Po-Chou Chen

IPC分类号： G11C16/04 ,  H01L29/792 ,  H01L21/336

CPC分类号： G11C16/0475 ,  H01L27/11568 ,  H01L29/42352 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

摘要： The memory device is described, which includes a substrate, a conductive layer, a plurality of charge storage layers and a plurality of doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layers are disposed between the substrate and the conductive layer in the trenches respectively, wherein the charge storage layers are separated from each other. The doped regions are configured in the substrate under bottoms of the trenches, respectively.

摘要翻译： 描述了存储器件，其包括衬底，导电层，多个电荷存储层和多个掺杂区域。 衬底具有形成在其中的多个沟槽。 导电层设置在基板上并填充沟槽。 电荷存储层分别设置在沟槽中的衬底和导电层之间，其中电荷存储层彼此分离。 掺杂区域分别配置在沟槽底部的衬底中。

公开(公告)号：US20120127795A1

公开(公告)日：2012-05-24

申请号：US12949076

申请日：2010-11-18

申请人： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L29/792

CPC分类号： H01L21/28282 ,  G11C16/0475 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/7923

摘要： A non-volatile memory and a manufacturing method thereof and a method for operating a memory cell are provided. The non-volatile memory includes a substrate, first and second doped regions, a charged-trapping structure, first and second gates and an inter-gate insulation layer. The first and second doped regions are disposed in the substrate and extend along a first direction. The first and second doped regions are arranged alternately. The charged-trapping structure is disposed on the substrate. The first and second gates are disposed on the charged-trapping structure. Each first gate is located above one of the first doped regions. The second gates extend along a second direction and are located above the second doped regions. The inter-gate insulation layer is disposed between the first gates and the second gates. Adjacent first and second doped regions and the first gate, the second gate and the charged-trapping structure therebetween define a memory cell.

摘要翻译： 提供一种非易失性存储器及其制造方法以及操作存储单元的方法。 非易失性存储器包括衬底，第一和第二掺杂区域，带电捕获结构，第一和第二栅极以及栅极间绝缘层。 第一和第二掺杂区域设置在衬底中并沿着第一方向延伸。 第一和第二掺杂区交替布置。 带电捕获结构设置在基板上。 第一和第二栅极设置在带电捕获结构上。 每个第一栅极位于第一掺杂区域之上。 第二栅极沿着第二方向延伸并且位于第二掺杂区域之上。 栅间绝缘层设置在第一栅极和第二栅极之间。 相邻的第一和第二掺杂区域和第一栅极，其间的第二栅极和带电捕获结构限定了存储单元。

公开(公告)号：US20120126307A1

公开(公告)日：2012-05-24

申请号：US12949092

申请日：2010-11-18

申请人： GUAN-WEI WU ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： GUAN-WEI WU ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L21/76232

摘要： A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The gate structure includes a charge storage structure, a gate and spacers.The charge storage structure is disposed on the substrate. The gate is disposed on the charge storage structure. The spacers are disposed on the sidewalls of the gate and the charge storage structure. The first doped region and the second doped region are respectively disposed in the substrate at two sides of the charge storage structure and at least located under the spacers. The isolation structures are respectively disposed in the substrate at two sides of the gate structure.

摘要翻译： 提供了一种非易失性存储器及其制造方法。 非易失性存储器包括衬底，栅极结构，第一掺杂区，第二掺杂区和一对隔离结构。 栅极结构设置在基板上。 栅极结构包括电荷存储结构，栅极和间隔物。 电荷存储结构设置在基板上。 栅极设置在电荷存储结构上。 间隔件设置在栅极和电荷存储结构的侧壁上。 第一掺杂区域和第二掺杂区域分别设置在电荷存储结构的两侧的基板中，并且至少位于间隔物之下。 隔离结构分别设置在栅极结构的两侧的基板中。

公开(公告)号：US08093665B2

公开(公告)日：2012-01-10

申请号：US12467479

申请日：2009-05-18

申请人： I-Chen Yang ,  Guan-Wei Wu ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： I-Chen Yang ,  Guan-Wei Wu ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/66636 ,  H01L29/665 ,  H01L29/7834

摘要： A semiconductor device is described, which includes a substrate, a gate structure, doped regions and lightly doped regions. The substrate has a stepped upper surface, which includes a first surface, a second surface and a third surface. The second surface is lower than the first surface. The third surface connects the first surface and the second surface. The gate structure is disposed on the first surface. The doped regions are configured in the substrate at both sides of the gate structure and under the second surface. The lightly doped regions are configured in the substrate between the gate structure and the doped regions, respectively. Each lightly doped region includes a first part and a second part connecting with each other. The first part is disposed under the second surface, and the second part is disposed under the third surface.

摘要翻译： 描述了一种半导体器件，其包括衬底，栅极结构，掺杂区域和轻掺杂区域。 基板具有阶梯状的上表面，其包括第一表面，第二表面和第三表面。 第二表面低于第一表面。 第三表面连接第一表面和第二表面。 栅极结构设置在第一表面上。 掺杂区域在栅极结构的两侧和第二表面的下方在衬底中配置。 轻掺杂区域分别配置在栅极结构和掺杂区域之间的衬底中。 每个轻掺杂区域包括彼此连接的第一部分和第二部分。 第一部分设置在第二表面下方，第二部分设置在第三表面下。