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    Computer system, program, and method for assigning computational resource to be used in simulation
    1.
    发明授权
    Computer system, program, and method for assigning computational resource to be used in simulation 有权
    用于分配计算资源的计算机系统，程序和方法用于仿真

    公开(公告)号：US09037448B2

    公开(公告)日：2015-05-19

    申请号：US13387243

    申请日：2010-07-16

    申请人： Yasuhiro Ito ,  Yasuo Sugure ,  Shigeru Oho ,  Hideaki Kurata

    发明人： Yasuhiro Ito ,  Yasuo Sugure ,  Shigeru Oho ,  Hideaki Kurata

    IPC分类号： G06F9/44 ,  G06F11/36 ,  G06F9/50

    CPC分类号： G06F11/3664 ,  G06F9/5055

    摘要： The cost necessary for introducing and maintaining a development environment that includes multiple simulators is suppressed, and a sharing of designing information is promoted, to make parameter adjustment of simulators easy. Provided is a service that unifies development environment on a computer provided with: a working computer system that can guarantee that there is no leaking of designing files; a user behavior monitoring system that collects utilization history of simulators or software, for each of the users, and selects development process of each of the users from the collected information; and a dynamic computational-resource distribution system that can conduct an automatic optimization of a complex simulation configuration, from information collected by the aforementioned user behavior monitoring system.

    摘要翻译： 引入和维护包含多个模拟器的开发环境所需的成本被抑制，并且提高了设计信息的共享，从而使模拟器的参数调整变得容易。 提供了一种将计算机上的开发环境统一起来的服务，它具有：可以保证设计文件不泄漏的工作计算机系统; 用户行为监控系统，用于为每个用户收集模拟器或软件的利用历史，并从收集的信息中选择每个用户的开发过程; 以及动态计算资源分配系统，可以从上述用户行为监控系统收集的信息中进行复杂模拟配置的自动优化。

    Computer System, Program, and Method for Assigning Computational Resource to be Used in Simulation
    2.
    发明申请
    Computer System, Program, and Method for Assigning Computational Resource to be Used in Simulation 有权
    计算机系统，程序和分配用于仿真的计算资源的方法

    公开(公告)号：US20120123764A1

    公开(公告)日：2012-05-17

    申请号：US13387243

    申请日：2010-07-16

    申请人： Yasuhiro Ito ,  Yasuo Sugure ,  Shigeru Oho ,  Hideaki Kurata

    发明人： Yasuhiro Ito ,  Yasuo Sugure ,  Shigeru Oho ,  Hideaki Kurata

    IPC分类号： G06F17/50

    CPC分类号： G06F11/3664 ,  G06F9/5055

    摘要： The cost necessary for introducing and maintaining a development environment that includes multiple simulators is suppressed, and a sharing of designing information is promoted, to make parameter adjustment of simulators easy. Provided is a service that unifies development environment on a computer provided with: a working computer system that can guarantee that there is no leaking of designing files; a user behavior monitoring system that collects utilization history of simulators or software, for each of the users, and selects development process of each of the users from the collected information; and a dynamic computational-resource distribution system that can conduct an automatic optimization of a complex simulation configuration, from information collected by the aforementioned user behavior monitoring system.

    摘要翻译： 引入和维护包含多个模拟器的开发环境所需的成本被抑制，并且提高了设计信息的共享，从而使模拟器的参数调整变得容易。 提供了一种将计算机上的开发环境统一起来的服务，它具有：可以保证设计文件不泄漏的工作计算机系统; 用户行为监控系统，用于为每个用户收集模拟器或软件的利用历史，并从收集的信息中选择每个用户的开发过程; 以及动态计算资源分配系统，可以从上述用户行为监控系统收集的信息中进行复杂模拟配置的自动优化。

    Measurement Device
    3.
    发明申请
    Measurement Device 有权
    测量装置

    公开(公告)号：US20130113644A1

    公开(公告)日：2013-05-09

    申请号：US13809746

    申请日：2010-07-14

    申请人： Tatsuo Nakagawa ,  Akihiko Hyodo ,  Hideaki Kurata ,  Shigeru Oho

    发明人： Tatsuo Nakagawa ,  Akihiko Hyodo ,  Hideaki Kurata ,  Shigeru Oho

    IPC分类号： G01S13/08

    CPC分类号： G01S13/08 ,  G01F23/284 ,  G01F23/2845 ,  G01S13/04 ,  G01S13/751

    摘要： Disclosed is a measurement device that can accurately measure size, position, the presence of an object, and the like by means of a simple and low-cost method. Specifically, disclosed is a measurement device that is provided with: a transmitter that transmits radio waves; a vibrating surface that vibrates mechanically; a receiver that receives radio waves; and a controller that transmits radio waves from the transmitter, and on the basis of the signal of the radio waves reflected by the vibrating surface and received by the receiver, outputs information about a measured object on the pathway between the transmitter and the receiver with the vibrating surface therebetween.

    摘要翻译： 公开了一种可以通过简单且低成本的方法精确地测量尺寸，位置，物体的存在等的测量装置。 具体地，公开了一种测量装置，其具备：发送无线电波的发送机; 机械振动的振动表面; 接收无线电波的接收机; 以及控制器，其从发射机发送无线电波，并且基于由振动面反射并由接收机接收的无线电波的信号，在发射机和接收机之间的路径上输出关于测量对象的信息， 振动表面。

    Measurement device
    4.
    发明授权
    Measurement device 有权
    测量装置

    公开(公告)号：US09194944B2

    公开(公告)日：2015-11-24

    申请号：US13809746

    申请日：2010-07-14

    申请人： Tatsuo Nakagawa ,  Akihiko Hyodo ,  Hideaki Kurata ,  Shigeru Oho

    发明人： Tatsuo Nakagawa ,  Akihiko Hyodo ,  Hideaki Kurata ,  Shigeru Oho

    IPC分类号： G01S13/04 ,  G01S13/08 ,  G01F23/284 ,  G01S13/75 ,  G01S13/00 ,  G01F23/00

    CPC分类号： G01S13/08 ,  G01F23/284 ,  G01F23/2845 ,  G01S13/04 ,  G01S13/751

    摘要： Disclosed is a measurement device that can accurately measure size, position, the presence of an object, and the like by means of a simple and low-cost method. Specifically, disclosed is a measurement device that is provided with: a transmitter that transmits radio waves; a vibrating surface that vibrates mechanically; a receiver that receives radio waves; and a controller that transmits radio waves from the transmitter, and on the basis of the signal of the radio waves reflected by the vibrating surface and received by the receiver, outputs information about a measured object on the pathway between the transmitter and the receiver with the vibrating surface therebetween.

    摘要翻译： 公开了一种可以通过简单且低成本的方法精确地测量尺寸，位置，物体的存在等的测量装置。 具体地，公开了一种测量装置，其具备：发送无线电波的发送机; 机械振动的振动表面; 接收无线电波的接收机; 以及控制器，其从发射机发送无线电波，并且基于由振动面反射并由接收机接收的无线电波的信号，在发射机和接收机之间的路径上输出关于测量对象的信息， 振动表面。

    Semiconductor memory device and manufacturing method of the same
    5.
    发明授权
    Semiconductor memory device and manufacturing method of the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US07969760B2

    公开(公告)日：2011-06-28

    申请号：US11790590

    申请日：2007-04-26

    申请人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

    发明人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

    IPC分类号： G11C5/06

    CPC分类号： H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

    摘要： The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.

    摘要翻译： 本发明提供一种相对于数据线具有减小的面积损失的电压施加结构。 形成在p型阱区中的全局数据线和局部数据线的布线经由选择晶体管连接。 在选择晶体管的栅电极上形成两条选择线。 一个选择线电连接到选择晶体管的栅电极，然而另一选择线不连接到选择晶体管。 也就是说，在选择线和栅电极之间形成绝缘膜。 如上所述，在一个选择晶体管上设置两条比栅极长度短的选择线。 选择线被构造成连接到另一个选择晶体管。

    Semiconductor memory device comprising controllable threshold voltage dummy memory cells
    7.
    发明申请
    Semiconductor memory device comprising controllable threshold voltage dummy memory cells 审中-公开
    半导体存储器件包括可控阈值电压虚拟存储器单元

    公开(公告)号：US20080055983A1

    公开(公告)日：2008-03-06

    申请号：US11976299

    申请日：2007-10-23

    申请人： Hideaki Kurata ,  Yoshihiro Ikeda ,  Masahiro Shimizu ,  Kenji Kozakai ,  Satoshi Noda

    发明人： Hideaki Kurata ,  Yoshihiro Ikeda ,  Masahiro Shimizu ,  Kenji Kozakai ,  Satoshi Noda

    IPC分类号： G11C16/28

    CPC分类号： G11C8/14

    摘要： An object of the present invention is to provide a semiconductor memory device capable of preventing a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitch of word lines at an end of a memory block. Plural dummy word lines are disposed at an end of a memory block, a word driver is mounted for the dummy word line to control the threshold voltage of a dummy memory cell formed below the dummy word line. Also at the time of operating a memory area for storing data from the outside, a bias is applied to the dummy word line. The invention can prevent a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitches of word lines at an end of a memory block, and realize high yield and reliably operation.

    摘要翻译： 本发明的目的是提供一种半导体存储器件，其能够防止由于字线的下降引起的缺陷以及由于在存储器块的端部处的字线的间距的干扰而导致的图案精度的劣化。 多个虚拟字线设置在存储器块的末端，为虚拟字线安装字驱动器以控制形成在虚拟字线下面的虚拟存储器单元的阈值电压。 此外，在操作用于存储来自外部的数据的存储区域时，偏置被施加到虚拟字线。 本发明可以防止由于字线下降引起的缺陷和由于记忆块末端的字线的间距的干扰导致的图案精度的劣化，并且实现高产率和可靠的操作。

    Semiconductor memory device and manufacturing method of the same
    8.
    发明申请
    Semiconductor memory device and manufacturing method of the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20070285983A1

    公开(公告)日：2007-12-13

    申请号：US11790590

    申请日：2007-04-26

    申请人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

    发明人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

    IPC分类号： G11C11/34 ,  H01L21/336

    CPC分类号： H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

    摘要： The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.

    摘要翻译： 本发明提供一种相对于数据线具有减小的面积损失的电压施加结构。 形成在p型阱区中的全局数据线和局部数据线的布线经由选择晶体管连接。 在选择晶体管的栅电极上形成两条选择线。 一个选择线电连接到选择晶体管的栅电极，然而另一选择线不连接到选择晶体管。 也就是说，在选择线和栅电极之间形成绝缘膜。 如上所述，在一个选择晶体管上设置两条比栅极长度短的选择线。 选择线被构造成连接到另一个选择晶体管。

    Semiconductor intergrated circuit device and process for producing the same
    9.
    发明申请
    Semiconductor intergrated circuit device and process for producing the same 审中-公开
    半导体集成电路器件及其制造方法

    公开(公告)号：US20060275986A1

    公开(公告)日：2006-12-07

    申请号：US11499756

    申请日：2006-08-07

    申请人： Takashi Kobayashi ,  Yasushi Goto ,  Tokuo Kure ,  Hideaki Kurata ,  Hitoshi Kume ,  Katsutaka Kimura ,  Syunichi Saeki

    发明人： Takashi Kobayashi ,  Yasushi Goto ,  Tokuo Kure ,  Hideaki Kurata ,  Hitoshi Kume ,  Katsutaka Kimura ,  Syunichi Saeki

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/7881

    摘要： A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions 205 formed first conduction type well 201, floating gates 203b formed on semiconductor substrate 200 through an insulator film 202, control gates 211a formed on floating gates 203b through nitrogen-introduced silicon oxide film 210a and third gates 207a different from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gates 207a thus formed is made lower than that of floating gates 203b, has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.

    摘要翻译： 具有第三栅极的半导体集成电路器件包括形成在第一导电型阱201的第二导电型源极/漏极扩散层区域205，通过绝缘膜202形成在半导体衬底200上的浮置栅极203b，形成在浮动栅极203上的控制栅极211a b通过氮引入氧化硅膜210a和与通过半导体衬底，浮栅，控制栅极和绝缘膜形成的浮栅和控制栅极不同的第三栅极207a，其中第三栅极形成为 填充在垂直方向上存在的浮动栅极与字线和沟道之间的间隙以及如此形成的第三栅极207a的高度低于浮动栅极203b的高度，具有改善的存储单元尺寸和操作速度的降低和改进 编程/擦除周期后的可靠性。