公开(公告)号：US20070255872A1

公开(公告)日：2007-11-01

申请号：US11780031

申请日：2007-07-19

申请人： Yasuhiro TAWARA ,  Junichi Nishimoto

发明人： Yasuhiro TAWARA ,  Junichi Nishimoto

IPC分类号： G06F13/00

CPC分类号： G06F13/404

摘要： A technology for allowing easy handling of a change in the address range of the subject of access or any of bus masters is provided. There is provided an address monitor unit including a table which is shared among a plurality of bus masters and stores therein access right information that has been preset in correspondence to the subject of access and to address information corresponding thereto and capable of determining, by referencing the table, the presence or absence of an access right for each of the bus masters based on the subject-of-access information of each of the bus masters and on address information outputted from the bus master. Since the table is shared among the plurality of bus masters, when the address range of the subject of access or any of the bus masters is changed, the table may be rewritten appropriately. This allows, when a plurality of bus masters are connected to a common bus, easy handling of a change in the address range of the subject of access or any of the bus masters.

摘要翻译： 提供了一种允许容易地处理访问主体的地址范围或任何总线主机的改变的技术。 提供了一种地址监视器单元，包括在多个总线主机之间共享的表，其中存储对应于访问对象预先设置的访问权限信息和与其对应的地址信息，并且能够通过参考 基于每个总线主机的访问主体信息以及从总线主机输出的地址信息，每个总线主机的访问权限的存在或不存在。 由于在多个总线主机之间共享表，当访问对象的地址范围或任何总线主机的地址范围改变时，可以适当地重写表。 这允许当多个总线主机连接到公共总线时，容易地处理访问对象的地址范围的变化或任何总线主控器。

公开(公告)号：US20120198257A1

公开(公告)日：2012-08-02

申请号：US13362734

申请日：2012-01-31

申请人： Hitoshi YAMAMOTO ,  Akio IDEHARA ,  Yasuhiro TAWARA

发明人： Hitoshi YAMAMOTO ,  Akio IDEHARA ,  Yasuhiro TAWARA

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Timers #0 through #3 are each supplied with a period for prohibiting a change in a power supply voltage. An OS #A or an OS #B determines necessity to change an operating frequency for a CPU core corresponding to any of the timers #0 through #3 when the timer exceeds the prohibition period. It is determined whether it is necessary to change a power supply voltage supplied to CPU cores #0 through #3 when the OS #A or the OS #B determines necessity to change an operating frequency. When it is determined that a power supply voltage needs to be changed, a power supply voltage change portion 20 changes the power supply voltage supplied to the CPU cores #0 through #3. Therefore, it is possible to improve the processing efficiency without needing to acquire inter-OS lock.

摘要翻译： 定时器＃0至＃3各自被提供有用于禁止电源电压改变的周期。 当定时器超过禁止期间时，OS #A或OS #B确定需要改变与任何定时器＃0至＃3相对应的CPU核心的工作频率。 当OS #A或OS #B确定需要改变操作频率时，确定是否需要改变提供给CPU核心＃0至＃3的电源电压。 当确定需要改变电源电压时，电源电压变化部分20改变提供给CPU核心＃0至＃3的电源电压。 因此，可以在不需要获取OS间锁定的情况下提高处理效率。