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321 条记录 (耗时 0.031 秒)

    Semiconductor memory with built-in cache
    3.
    发明授权
    Semiconductor memory with built-in cache 失效
    半导体内存具有内置缓存

    公开(公告)号：US5596521A

    公开(公告)日：1997-01-21

    申请号：US365970

    申请日：1994-12-29

    申请人： Yasuhiro Tanaka ,  Tetsuya Tanabe ,  Satoru Tanoi

    发明人： Yasuhiro Tanaka ,  Tetsuya Tanabe ,  Satoru Tanoi

    IPC分类号： G06F12/08 ,  G11C7/10 ,  G11C11/4096 ,  G11C15/04 ,  G11C15/00

    CPC分类号： G11C7/106 ,  G06F12/0893 ,  G11C11/4096 ,  G11C15/04 ,  G11C15/043 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C2207/2245

    摘要： A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.

    摘要翻译： 半导体存储器件具有用于存储数据的存储器单元，用于放大所存储的数据的读出放大器，以及可放置放大数据以用于快速调用的高速缓存单元。 高速缓存单元可以在存储单元刷新周期期间继续保持数据，从而允许快速访问缓存的数据。 高速缓存单元可以耦合到可以从读出放大器断开的列数据线，使得能够刷新存储器单元，同时缓存访问正在进行。 可以提供写入缓冲器，使得当高速缓存数据被替换时，旧的高速缓存数据可以被复制回存储器单元，同时正在访问新的高速缓存数据。

    Dynamic random access memory (DRAM) with cache and tag
    4.
    发明授权
    Dynamic random access memory (DRAM) with cache and tag 失效
    具有缓存和标签的动态随机存取存储器（DRAM）

    公开(公告)号：US5577223A

    公开(公告)日：1996-11-19

    申请号：US297450

    申请日：1994-08-29

    申请人： Satoru Tanoi ,  Yasuhiro Tanaka ,  Tetsuya Tanabe

    发明人： Satoru Tanoi ,  Yasuhiro Tanaka ,  Tetsuya Tanabe

    IPC分类号： G06F12/08 ,  G11C11/401 ,  G11C11/408 ,  G06F12/00

    CPC分类号： G11C11/4087 ,  G06F12/0893

    摘要： A dynamic RAM having a TAG address holding circuit in a TAG block in correspondence with one of a plurality of sub-arrays to hold the lower bits of an X (row) address. A block control circuit in the TAG block determines a "Hit" or "Miss" in accordance with the held address and a new X address in response to the sub-address and outputs a TAG determination signal. In response to the TAG judgment signal, a sub-array control circuit transfers a signal for access to the TAG block and a column sense amplifier. The column sense amplifier is utilized as a cache and data latched in the column sense amplifier are read out on a data bus when a "Hit" is determined.

    摘要翻译： 一种具有TAG块中的TAG地址保持电路的动态RAM，其与多个子阵列中的一个子阵列对应以保持X（行）地址的低位。 TAG块中的块控制电路根据所保存的地址确定“命中”或“小号”，并响应于子地址确定新的X地址并输出TAG确定信号。 响应于TAG判断信号，子阵列控制电路传送用于访问TAG块和列读出放大器的信号。 当确定“命中”时，列读出放大器用作高速缓存，并且锁存在列读出放大器中的数据在数据总线上读出。

    Semiconductor memory device and method of driving same
    5.
    发明授权
    Semiconductor memory device and method of driving same 失效
    半导体存储器件及其驱动方法

    公开(公告)号：US5511030A

    公开(公告)日：1996-04-23

    申请号：US296364

    申请日：1994-08-24

    申请人： Yasuhiro Tanaka ,  Tetsuya Tanabe ,  Satoru Tanoi

    发明人： Yasuhiro Tanaka ,  Tetsuya Tanabe ,  Satoru Tanoi

    IPC分类号： G11C11/401 ,  G11C7/12 ,  G11C7/18 ,  G11C11/409 ,  G11C7/00

    CPC分类号： G11C11/409 ,  G11C7/12 ,  G11C7/18

    摘要： A semiconductor memory device according to the present invention is constructed in such a manner that two first and second memory circuits are respectively electrically connected to one sense amplifier provided between the memory circuits through changeover elements and equalize elements are electrically connected to their corresponding bit line pairs included in the memory circuits. Owing to this construction, an operation for resetting the bit line pair in the first memory circuit and the sense amplifier after completion of access to the first memory circuit and an operation for reading data into the bit line pair in the second memory circuit can be performed so as to overlap each other in time. It is therefore possible to obtain quick-access to the second memory circuit.

    摘要翻译： 根据本发明的半导体存储器件被构造成使得两个第一和第二存储器电路分别通过切换元件电连接到设置在存储器电路之间的一个读出放大器，并且均衡元件电连接到它们对应的位线对 包含在存储器电路中。 由于这种结构，可以执行用于在完成对第一存储器电路的访问之后复位第一存储器电路中的位线对和读出放大器的操作以及用于将数据读入第二存储器电路中的位线对的操作 以便在时间上彼此重叠。 因此可以获得对第二存储器电路的快速访问。

    Semiconductor memory device having circuits for precharging and equalizing
    6.
    发明授权
    Semiconductor memory device having circuits for precharging and equalizing 失效
    具有用于预充电和均衡的电路的半导体存储器件

    公开(公告)号：US5477496A

    公开(公告)日：1995-12-19

    申请号：US371536

    申请日：1995-01-11

    申请人： Yasuhiro Tanaka ,  Tetsuya Tanabe

    发明人： Yasuhiro Tanaka ,  Tetsuya Tanabe

    IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C11/409 ,  G11C11/4094 ,  G11C7/00

    CPC分类号： G11C11/4094 ,  G11C7/12

    摘要： A semiconductor memory device includes first and second MOS transistors connecting a pair of data lines with a specific potential supplying node. A power transmitting circuit couples the specific potential supplying node with a power supply circuit of an equalizing potential after said first and second switching elements are made conductive. The power transmitting circuit isolates the specific potential supplying node from the power supply circuit when the equalization begins. As an alternative to the power transmitting circuit, a supplying circuit may be connected to supply a precharge potential to the specific potential supplying node when the equalization begins, and supply an equalizing potential to the specific potential supplying node when the switching elements are both turned on.

    摘要翻译： 半导体存储器件包括连接一对数据线与特定电位供给节点的第一和第二MOS晶体管。 在所述第一和第二开关元件导通之后，电力发送电路将特定电位供应节点与均衡电位的电源电路耦合。 当均衡开始时，电力传输电路将特定电位供应节点与电源电路隔离。 作为电力传输电路的替代方案，当均衡开始时，可​​以连接提供电路以向特定电位供应节点提供预充电电势，并且当开关元件都接通时，向特定电位供应节点提供均衡电位 。

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5652727A

    公开(公告)日：1997-07-29

    申请号：US681389

    申请日：1996-07-23

    申请人： Yasuhiro Tanaka ,  Tetsuya Tanabe

    发明人： Yasuhiro Tanaka ,  Tetsuya Tanabe

    IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C11/409 ,  G11C11/4094 ,  G11C7/00

    CPC分类号： G11C11/4094 ,  G11C7/12

    摘要： A semiconductor memory device includes first and second MOS transistors connecting a pair of data lines with a specific potential supplying node. A power transmitting circuit couples the specific potential supplying node with a power supply circuit of an equalizing potential after said first and second switching elements are made conductive. The power transmitting circuit isolates the specific potential supplying node from the power supply circuit when the equalization begins. As an alternative to the power transmitting circuit, a supplying circuit may be connected to supply a precharge potential to the specific potential supplying node when the equalization begins, and supply an equalizing potential to the specific potential supplying node when the switching elements are both turned on.

    摘要翻译： 半导体存储器件包括连接一对数据线与特定电位供给节点的第一和第二MOS晶体管。 在所述第一和第二开关元件导通之后，电力发送电路将特定电位供应节点与均衡电位的电源电路耦合。 当均衡开始时，电力传输电路将特定电位供应节点与电源电路隔离。 作为电力传输电路的替代方案，当均衡开始时，可​​以连接提供电路以向特定电位供应节点提供预充电电势，并且当开关元件都接通时，向特定电位供应节点提供均衡电位 。