公开(公告)号：US20100110213A1

公开(公告)日：2010-05-06

申请号：US12552680

申请日：2009-09-02

申请人： Katsuyuki KIMURA ,  Takashi MIYAMORI ,  Shunichi ISHIWATA ,  Takahisa WADA ,  Keiri NAKANISHI ,  Masato SUMIYOSHI ,  Yasuki TANABE ,  Ryuji HADA

发明人： Katsuyuki KIMURA ,  Takashi MIYAMORI ,  Shunichi ISHIWATA ,  Takahisa WADA ,  Keiri NAKANISHI ,  Masato SUMIYOSHI ,  Yasuki TANABE ,  Ryuji HADA

IPC分类号： H04N5/225 ,  G06T1/00

CPC分类号： G06T1/60 ,  H04N1/00931 ,  H04N1/2137 ,  H04N2101/00 ,  H04N2201/3287 ,  H04N2201/3292

摘要： An input unit that sequentially writes a digital image signal to be input in a first buffer while counting number of pixels of the digital image signal, and that writes the written digital image signal in a second buffer; and a command fetching/issuing unit that calculates a position of a pixel based on process delay information that is added to an image processing command and that indicates a delay amount required until image processing by the command is started since the input of the digital image signal, and a counter value indicating the number of pixels, and that issues the image processing command when the position of the pixel is in a valid area are included. Image processing is performed on pixels written in the second buffer based on the issued image processing command.

摘要翻译： 一种输入单元，其在计数所述数字图像信号的像素数量的同时，顺序地写入要输入的第一缓冲器的数字图像信号，并将所述写入的数字图像信号写入第二缓冲器; 以及命令获取/发布单元，其基于加到图像处理命令的处理延迟信息来计算像素的位置，并且指示由命令进行的图像处理之前所需的延迟量，从数字图像信号的输入开始 以及指示像素数的计数器值，并且当像素的位置在有效区域时发出图像处理命令。 基于发出的图像处理命令对写入第二缓冲器的像素进行图像处理。

公开(公告)号：US20110138371A1

公开(公告)日：2011-06-09

申请号：US12876599

申请日：2010-09-07

申请人： Yasuki TANABE ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Ryuji Hada

发明人： Yasuki TANABE ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Ryuji Hada

IPC分类号： G06F9/45

CPC分类号： G06F8/445

摘要： According to an embodiment, a compiling device compiling a source program written so as to use a frame memory includes a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data processed by the process tasks. The compiling device also includes a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data and an instruction code converter configured to convert the plurality of process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes.

摘要翻译： 根据一个实施例，编译用于使用帧存储器的源程序的编译装置包括：处理延迟量计算器，被配置为基于源程序的处理状态计算源程序中的多个处理任务之间的各个处理延迟量; 由进程任务处理的数据片段。 编译装置还包括行存储量计算器，其被配置为基于处理任务读取数据的帧存储器的访问范围来计算每个处理任务所需的各行行存储器大小，以及指令代码转换器，被配置为转换 基于处理延迟量和行存储器大小，可以在流水线中执行的指令代码的多个处理任务。

公开(公告)号：US20120288205A1

公开(公告)日：2012-11-15

申请号：US13208143

申请日：2011-08-11

申请人： Yasuki TANABE ,  Takashi MIYAMORI ,  Katsuyuki KIMURA

发明人： Yasuki TANABE ,  Takashi MIYAMORI ,  Katsuyuki KIMURA

IPC分类号： G06K9/68

CPC分类号： G06K9/68 ,  G06T1/60

摘要： According to one embodiment, an image processing apparatus connectable to a main memory in which a plurality of pixel values of unconverted image is stored and a cache memory including a plurality of cache blocks. The apparatus includes a counter, a coordinate determination module, a memory controller, a cache access module, a pixel value calculator, and an output module. The counter determines a coordinate within converted image according to a predetermined execution sequence. The coordinate determination module determines a plurality of coordinates within unconverted image of the pixel values of unconverted image necessary to calculate a pixel value of converted image corresponding to the coordinate within converted image. The memory controller transfers the pixel values of unconverted image stored in the main memory to the cache blocks corresponding to each of the coordinates within unconverted image. The cache access module reads out all the pixel values of unconverted image necessary to calculate the pixel value of converted image from the cache blocks. The pixel value calculator calculates the pixel value of converted image by referring to the pixel values of unconverted image read out by the cache access module. The output module outputs the pixel value of converted image.

摘要翻译： 根据一个实施例，可连接到其中存储未转换图像的多个像素值的主存储器的图像处理设备和包括多个高速缓存块的高速缓存存储器。 该装置包括计数器，坐标确定模块，存储器控制器，高速缓存存取模块，像素值计算器和输出模块。 计数器根据预定的执行顺序确定转换图像内的坐标。 坐标确定模块确定未转换图像中的未转换图像的像素值之间的多个坐标，以计算与转换图像内的坐标对应的转换图像的像素值所必需的。 存储器控制器将存储在主存储器中的未转换图像的像素值传送到对应于未转换图像中的每个坐标的高速缓存块。 缓存访问模块从高速缓存块读出计算转换后的图像的像素值所需的未转换图像的所有像素值。 像素值计算器通过参照由高速缓存存取模块读出的未转换图像的像素值来计算转换图像的像素值。 输出模块输出转换图像的像素值。