公开(公告)号：US08345113B2

公开(公告)日：2013-01-01

申请号：US12512593

申请日：2009-07-30

申请人： Keiri Nakanishi ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Masato Sumiyoshi ,  Yasuki Tanabe ,  Ryuji Hada

发明人： Keiri Nakanishi ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Masato Sumiyoshi ,  Yasuki Tanabe ,  Ryuji Hada

IPC分类号： H04N5/228

CPC分类号： H04N5/77 ,  G06F9/30043 ,  G06F9/35 ,  G06F9/355

摘要： An image processing apparatus has: a data memory configured to store image data; an RP register configured to hold a two-dimensional address indicating a position of an RP in a frame of image data; and an RP control section configured to control the two-dimensional address held by the RP register on the basis of the width and height of the frame. Furthermore, the image processing apparatus has an address calculation unit configured to, when reading target pixel data is read from the data memory on the basis of an instruction code provided with a field for specifying a two-dimensional relative position from the RP by a combination of two immediate values, calculate an address at which the reading target pixel data is stored, on the basis of the two-dimensional address, the combination of immediate values and the width of the frame.

摘要翻译： 图像处理装置具有：数据存储器，被配置为存储图像数据; RP寄存器，被配置为保存指示图像数据的帧中的RP的位置的二维地址; 以及RP控制部，被配置为基于帧的宽度和高度来控制由RP寄存器保持的二维地址。 此外，图像处理装置具有地址计算单元，其被配置为当基于具有用于通过组合从RP指定二维相对位置的字段的指令代码从数据存储器读取目标像素数据时， 基于二维地址，立即值的组合和帧的宽度，计算存储读取目标像素数据的地址。

公开(公告)号：US20100110289A1

公开(公告)日：2010-05-06

申请号：US12540798

申请日：2009-08-13

申请人： Yasuki Tanabe ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Ryuji Hada

发明人： Yasuki Tanabe ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Ryuji Hada

IPC分类号： G06T1/00 ,  H04N5/04

CPC分类号： G06T1/20

摘要： An image processor includes a video input unit that counts the number of input pixel data and a command fetch/issue unit calculates, when a command including information concerning a relative position register in which a delay amount from input of pixel data until execution of a command is stored is fetched, a pixel position of processing target pixel data based on the delay amount and a count result and determines, based on the calculated pixel position, whether signal processing should be performed or specifies an operand used in arithmetic operation.

摘要翻译： 图像处理器包括对输入像素数据的数量进行计数的视频输入单元，并且命令获取/发出单元计算包括关于相对位置寄存器的信息的命令，其中从输入像素数据到执行命令的延迟量 取出存储的像素位置，基于延迟量的处理对象像素数据的像素位置和计数结果，并且基于计算出的像素位置确定是否应执行信号处理或指定算术运算中使用的操作数。

公开(公告)号：US08888296B2

公开(公告)日：2014-11-18

申请号：US13421540

申请日：2012-03-15

申请人： Yutaka Ota ,  Ryuji Hada

发明人： Yutaka Ota ,  Ryuji Hada

IPC分类号： G03B21/14 ,  G09G3/00 ,  G06T1/20 ,  H04N9/31 ,  G09G5/39 ,  G06T1/60

CPC分类号： G03B21/147 ,  G06T1/20 ,  G06T1/60 ,  G09G3/002 ,  G09G5/39 ,  G09G2340/04 ,  H04N9/312 ,  H04N9/3179 ,  H04N9/3185 ,  H04N9/3188

摘要： A projector is provided with: an input line memory which holds an input image signal corresponding to one line; an image processor which generates an intermediate image signal correction-processed according to distortion of a projection lens, using the input image signal transferred from the input line memory; an output line memory which holds the intermediate image signal corresponding to one line; and an LCOS which guides light radiated from a light source to the projection lens in accordance with the intermediate image signal. The image processor is provided with an input supplementation buffer which stores the input image signals of a plurality of lines, an input data buffer which stores input image signals required to generate the intermediate image signal corresponding to one line, and a number-of-supplementary-lines calculator which calculates the number of supplementary lines of the input image signals.

摘要翻译： 投影仪具有：保持对应于一行的输入图像信号的输入行存储器; 图像处理器，使用从输入行存储器传送的输入图像信号，生成根据投影透镜的失真进行了校正处理的中间图像信号; 保持对应于一行的中间图像信号的输出行存储器; 以及根据中间图像信号将从光源照射的光引导到投影透镜的LCOS。 图像处理器设置有存储多条线的输入图像信号的输入补充缓冲器，存储生成对应于一行的中间图像信号所需的输入图像信号的输入数据缓冲器，以及补充数量 线计算器，其计算输入图像信号的补充行数。

公开(公告)号：US20110138371A1

公开(公告)日：2011-06-09

申请号：US12876599

申请日：2010-09-07

申请人： Yasuki TANABE ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Ryuji Hada

发明人： Yasuki TANABE ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Ryuji Hada

IPC分类号： G06F9/45

CPC分类号： G06F8/445

摘要： According to an embodiment, a compiling device compiling a source program written so as to use a frame memory includes a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data processed by the process tasks. The compiling device also includes a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data and an instruction code converter configured to convert the plurality of process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes.

摘要翻译： 根据一个实施例，编译用于使用帧存储器的源程序的编译装置包括：处理延迟量计算器，被配置为基于源程序的处理状态计算源程序中的多个处理任务之间的各个处理延迟量; 由进程任务处理的数据片段。 编译装置还包括行存储量计算器，其被配置为基于处理任务读取数据的帧存储器的访问范围来计算每个处理任务所需的各行行存储器大小，以及指令代码转换器，被配置为转换 基于处理延迟量和行存储器大小，可以在流水线中执行的指令代码的多个处理任务。

公开(公告)号：US08730250B2

公开(公告)日：2014-05-20

申请号：US12540798

申请日：2009-08-13

申请人： Yasuki Tanabe ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Ryuji Hada

发明人： Yasuki Tanabe ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Ryuji Hada

IPC分类号： G09G5/02

CPC分类号： G06T1/20

摘要： An image processor includes a video input unit that counts the number of input pixel data and a command fetch/issue unit calculates, when a command including information concerning a relative position register in which a delay amount from input of pixel data until execution of a command is stored is fetched, a pixel position of processing target pixel data based on the delay amount and a count result and determines, based on the calculated pixel position, whether signal processing should be performed or specifies an operand used in arithmetic operation.

摘要翻译： 图像处理器包括对输入像素数据的数量进行计数的视频输入单元，并且命令获取/发出单元计算包括关于相对位置寄存器的信息的命令，其中从输入像素数据到执行命令的延迟量 取出存储的像素位置，基于延迟量的处理对象像素数据的像素位置和计数结果，并且基于计算出的像素位置确定是否应执行信号处理或指定算术运算中使用的操作数。

公开(公告)号：US08413123B2

公开(公告)日：2013-04-02

申请号：US12876599

申请日：2010-09-07

申请人： Yasuki Tanabe ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Ryuji Hada

发明人： Yasuki Tanabe ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Ryuji Hada

IPC分类号： G06F9/45

CPC分类号： G06F8/445

摘要： According to an embodiment, a compiling device compiling a source program written so as to use a frame memory includes a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data processed by the process tasks. The compiling device also includes a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data and an instruction code converter configured to convert the plurality of process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes.

摘要翻译： 根据一个实施例，编译用于使用帧存储器的源程序的编译装置包括：处理延迟量计算器，被配置为基于源程序的处理状态计算源程序中的多个处理任务之间的各个处理延迟量; 由进程任务处理的数据片段。 编译装置还包括行存储量计算器，其被配置为基于处理任务读取数据的帧存储器的访问范围来计算每个处理任务所需的各行行存储器大小，以及指令代码转换器，被配置为转换 基于处理延迟量和行存储器大小，可以在流水线中执行的指令代码的多个处理任务。

公开(公告)号：US20130069961A1

公开(公告)日：2013-03-21

申请号：US13421540

申请日：2012-03-15

申请人： Yutaka Ota ,  Ryuji Hada

发明人： Yutaka Ota ,  Ryuji Hada

IPC分类号： G09G5/39 ,  G06T1/20

CPC分类号： G03B21/147 ,  G06T1/20 ,  G06T1/60 ,  G09G3/002 ,  G09G5/39 ,  G09G2340/04 ,  H04N9/312 ,  H04N9/3179 ,  H04N9/3185 ,  H04N9/3188

摘要： A projector of an embodiment is provided with: an input line memory which holds an input image signal corresponding to one line; an image processor which generates an intermediate image signal correction-processed according to distortion of a projection lens, using the input image signal transferred from the input line memory; an output line memory which holds the intermediate image signal corresponding to one line; and an LCOS which guides light radiated from a light source to the projection lens in accordance with the intermediate image signal. The image processor is provided with an input supplementation buffer which stores the input image signals of a plurality of lines, an input data buffer which stores input image signals required to generate the intermediate image signal corresponding to one line, and a number-of-supplementary-lines calculator which calculates the number of supplementary lines of the input image signals.

摘要翻译： 实施例的投影仪具有：保持对应于一行的输入图像信号的输入行存储器; 图像处理器，使用从输入行存储器传送的输入图像信号，生成根据投影透镜的失真进行了校正处理的中间图像信号; 保持对应于一行的中间图像信号的输出行存储器; 以及根据中间图像信号将从光源照射的光引导到投影透镜的LCOS。 图像处理器设置有存储多条线的输入图像信号的输入补充缓冲器，存储生成对应于一行的中间图像信号所需的输入图像信号的输入数据缓冲器，以及补充数量 线计算器，其计算输入图像信号的补充行数。

公开(公告)号：US08176290B2

公开(公告)日：2012-05-08

申请号：US12482876

申请日：2009-06-11

申请人： Takahisa Wada ,  Katsuyuki Kimura ,  Shunichi Ishiwata ,  Takashi Miyamori ,  Ryuji Hada ,  Keiri Nakanishi ,  Yasuki Tanabe ,  Masato Sumiyoshi

发明人： Takahisa Wada ,  Katsuyuki Kimura ,  Shunichi Ishiwata ,  Takashi Miyamori ,  Ryuji Hada ,  Keiri Nakanishi ,  Yasuki Tanabe ,  Masato Sumiyoshi

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F15/76 ,  G06F7/00 ,  G06F17/00

CPC分类号： G06F9/342 ,  G06F12/1441

摘要： A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an address of a first memory region by the processor is matched with the write-data requested to be written into the address of the second memory region, and if the read-data is matched with the write-data, prevents the write-data from being written into the address of the second memory region.

摘要翻译： 存储器控制器在接收到将写入数据写入由处理器发出的第二存储器区域的地址的写入请求时，确定由处理器请求从第一存储器区域的地址请求的读取数据是否与 写入数据被请求写入第二存储器区域的地址，并且如果读取数据与写入数据匹配，则防止将写入数据写入第二存储器区域的地址。

公开(公告)号：US20100211758A1

公开(公告)日：2010-08-19

申请号：US12648769

申请日：2009-12-29

申请人： Masato Sumiyoshi ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Keiri Nakanishi ,  Yasuki Tanabe ,  Ryuji Hada

发明人： Masato Sumiyoshi ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Keiri Nakanishi ,  Yasuki Tanabe ,  Ryuji Hada

IPC分类号： G06F9/312 ,  G06F9/445 ,  G06F9/46 ,  G06F12/00 ,  G06F9/34

CPC分类号： G06F9/383 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/345

摘要： A microprocessor that can perform sequential processing in data array unit includes: a load store unit that loads, when a fetched instruction is a load instruction for data, a data sequence including designated data from a data memory in memory width unit and specifies, based on an analysis result of the instruction, data scheduled to be designated in a load instruction in future; and a data temporary storage unit that stores use-scheduled data as the data specified by the load store unit.

摘要翻译： 可以在数据阵列单元中执行顺序处理的微处理器包括：加载存储单元，当获取的指令是数据的加载指令时，加载来自存储器宽度单元中的数据存储器的指定数据的数据序列，并基于 该指令的分析结果，将来被安排在加载指令中指定的数据; 以及数据临时存储单元，其将使用调度数据存储为由所述加载存储单元指定的数据。

公开(公告)号：US20100030978A1

公开(公告)日：2010-02-04

申请号：US12511305

申请日：2009-07-29

申请人： Ryuji HADA ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Yasuki Tanabe

发明人： Ryuji HADA ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Yasuki Tanabe

IPC分类号： G06F12/00

CPC分类号： H04L49/901 ,  G09G5/42

摘要： A memory controller controls a memory access to each memory region out of one or more memory regions in SIMD unit. The memory controller includes: a pointer-calculation hardware unit that increments by unit SIMD a value of an access control pointer corresponding to each of the memory regions at different timings corresponding to an access mode set beforehand in each memory region; and a memory-access-control hardware unit that calculates an access destination address in each of the memory regions based on a value of an access control pointer in the memory region, and causes a memory access in SIMD unit to be performed to the calculated access destination address.

摘要翻译： 存储器控制器控制对SIMD单元中的一个或多个存储器区域中的每个存储器区域的存储器访问。 存储器控制器包括：指针计算硬件单元，其以与每个存储器区域中预先设置的访问模式相对应的不同定时，以单位SIMD为单位增加与每个存储区域对应的访问控制指针的值; 以及存储器访问控制硬件单元，其基于存储区域中的访问控制指针的值来计算每个存储器区域中的访问目的地地址，并且使SIMD单元中的存储器访问对所计算的访问执行 目的地址。