公开(公告)号：US08345113B2

公开(公告)日：2013-01-01

申请号：US12512593

申请日：2009-07-30

申请人： Keiri Nakanishi ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Masato Sumiyoshi ,  Yasuki Tanabe ,  Ryuji Hada

发明人： Keiri Nakanishi ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Masato Sumiyoshi ,  Yasuki Tanabe ,  Ryuji Hada

IPC分类号： H04N5/228

CPC分类号： H04N5/77 ,  G06F9/30043 ,  G06F9/35 ,  G06F9/355

摘要： An image processing apparatus has: a data memory configured to store image data; an RP register configured to hold a two-dimensional address indicating a position of an RP in a frame of image data; and an RP control section configured to control the two-dimensional address held by the RP register on the basis of the width and height of the frame. Furthermore, the image processing apparatus has an address calculation unit configured to, when reading target pixel data is read from the data memory on the basis of an instruction code provided with a field for specifying a two-dimensional relative position from the RP by a combination of two immediate values, calculate an address at which the reading target pixel data is stored, on the basis of the two-dimensional address, the combination of immediate values and the width of the frame.

摘要翻译： 图像处理装置具有：数据存储器，被配置为存储图像数据; RP寄存器，被配置为保存指示图像数据的帧中的RP的位置的二维地址; 以及RP控制部，被配置为基于帧的宽度和高度来控制由RP寄存器保持的二维地址。 此外，图像处理装置具有地址计算单元，其被配置为当基于具有用于通过组合从RP指定二维相对位置的字段的指令代码从数据存储器读取目标像素数据时， 基于二维地址，立即值的组合和帧的宽度，计算存储读取目标像素数据的地址。

公开(公告)号：US20120288205A1

公开(公告)日：2012-11-15

申请号：US13208143

申请日：2011-08-11

申请人： Yasuki TANABE ,  Takashi MIYAMORI ,  Katsuyuki KIMURA

发明人： Yasuki TANABE ,  Takashi MIYAMORI ,  Katsuyuki KIMURA

IPC分类号： G06K9/68

CPC分类号： G06K9/68 ,  G06T1/60

摘要： According to one embodiment, an image processing apparatus connectable to a main memory in which a plurality of pixel values of unconverted image is stored and a cache memory including a plurality of cache blocks. The apparatus includes a counter, a coordinate determination module, a memory controller, a cache access module, a pixel value calculator, and an output module. The counter determines a coordinate within converted image according to a predetermined execution sequence. The coordinate determination module determines a plurality of coordinates within unconverted image of the pixel values of unconverted image necessary to calculate a pixel value of converted image corresponding to the coordinate within converted image. The memory controller transfers the pixel values of unconverted image stored in the main memory to the cache blocks corresponding to each of the coordinates within unconverted image. The cache access module reads out all the pixel values of unconverted image necessary to calculate the pixel value of converted image from the cache blocks. The pixel value calculator calculates the pixel value of converted image by referring to the pixel values of unconverted image read out by the cache access module. The output module outputs the pixel value of converted image.

摘要翻译： 根据一个实施例，可连接到其中存储未转换图像的多个像素值的主存储器的图像处理设备和包括多个高速缓存块的高速缓存存储器。 该装置包括计数器，坐标确定模块，存储器控制器，高速缓存存取模块，像素值计算器和输出模块。 计数器根据预定的执行顺序确定转换图像内的坐标。 坐标确定模块确定未转换图像中的未转换图像的像素值之间的多个坐标，以计算与转换图像内的坐标对应的转换图像的像素值所必需的。 存储器控制器将存储在主存储器中的未转换图像的像素值传送到对应于未转换图像中的每个坐标的高速缓存块。 缓存访问模块从高速缓存块读出计算转换后的图像的像素值所需的未转换图像的所有像素值。 像素值计算器通过参照由高速缓存存取模块读出的未转换图像的像素值来计算转换图像的像素值。 输出模块输出转换图像的像素值。

公开(公告)号：US20100110289A1

公开(公告)日：2010-05-06

申请号：US12540798

申请日：2009-08-13

申请人： Yasuki Tanabe ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Ryuji Hada

发明人： Yasuki Tanabe ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Ryuji Hada

IPC分类号： G06T1/00 ,  H04N5/04

CPC分类号： G06T1/20

摘要： An image processor includes a video input unit that counts the number of input pixel data and a command fetch/issue unit calculates, when a command including information concerning a relative position register in which a delay amount from input of pixel data until execution of a command is stored is fetched, a pixel position of processing target pixel data based on the delay amount and a count result and determines, based on the calculated pixel position, whether signal processing should be performed or specifies an operand used in arithmetic operation.

摘要翻译： 图像处理器包括对输入像素数据的数量进行计数的视频输入单元，并且命令获取/发出单元计算包括关于相对位置寄存器的信息的命令，其中从输入像素数据到执行命令的延迟量 取出存储的像素位置，基于延迟量的处理对象像素数据的像素位置和计数结果，并且基于计算出的像素位置确定是否应执行信号处理或指定算术运算中使用的操作数。

公开(公告)号：US20090216932A1

公开(公告)日：2009-08-27

申请号：US12389822

申请日：2009-02-20

申请人： Katsuyuki KIMURA

发明人： Katsuyuki KIMURA

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： A data processing apparatus includes: a system bus; a processor connected to the system bus in slave connection, the processor having a command register configured to retain a DMA request command corresponding to a resource on the system bus and be accessed through the system bus; and a DMA controller connected to the system bus in bus-mastering connection, the DMA controller being configured to read out the DMA request command retained in the command register and control DMA transfer between the resource on the system bus and the processor based on the DMA request command.

摘要翻译： 一种数据处理装置，包括：系统总线; 在从属连接中连接到系统总线的处理器，所述处理器具有命令寄存器，所述命令寄存器被配置为保持与所述系统总线上的资源相对应的DMA请求命令并且通过所述系统总线访问; 以及在总线控制连接中连接到系统总线的DMA控制器，DMA控制器被配置为读出保存在命令寄存器中的DMA请求命令，并且基于DMA来控制系统总线上的资源与处理器之间的DMA传输 请求命令。

公开(公告)号：US20050289400A1

公开(公告)日：2005-12-29

申请号：US11148330

申请日：2005-06-09

申请人： Katsuyuki Kimura

发明人： Katsuyuki Kimura

IPC分类号： G06F11/00

CPC分类号： G06F11/3636

摘要： A trace analyzing apparatus, which includes a trace analysis table, an instruction reconstruction unit that reconstructs and sends an execution address and an instruction code of trace information, and an object code list storage unit, reads out an object code list and trace information, captures each piece of information in reverse order from the last stored address information stored in an address register, and then registers them in the trace analysis table.

摘要翻译： 一种跟踪分析装置，其包括跟踪分析表，重建并发送执行地址的指令重建单元和跟踪信息的指令代码以及目标代码列表存储单元，读取目标代码列表和跟踪信息，捕获 每条信息从存储在地址寄存器中的最后存储的地址信息的顺序相反，然后将其注册到跟踪分析表中。

公开(公告)号：US20100229162A1

公开(公告)日：2010-09-09

申请号：US12559962

申请日：2009-09-15

申请人： Ryuji HADA ,  Takashi Miyamori ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Takahisa Wada ,  Yasuki Tanabe ,  Katsuyuki Kimura ,  Shunichi Ishiwata

发明人： Ryuji HADA ,  Takashi Miyamori ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Takahisa Wada ,  Yasuki Tanabe ,  Katsuyuki Kimura ,  Shunichi Ishiwata

IPC分类号： G06F9/45 ,  G06F9/30

CPC分类号： G06F8/45 ,  G06F9/4494

摘要： A compiling apparatus includes an instruction-sequence-hierarchy-graph generating unit that generates an instruction sequence hierarchy graph by arraying unit graphs, to each of which a data path realized by a plurality of microinstructions included in one instruction sequence is to be allocated and in each of which function units included in a target processor are a node and a data line between the function units is an edge, to correspond to an execution order of a plurality of instruction sequences and by connecting arrayed unit graphs with an edge corresponding to a hardware path capable of establishing a data path across the instruction sequences; a data path allocating unit that allocates a data path to each of the unit graphs constituting the instruction sequence hierarchy graph; and an object program output unit that generates an instruction sequence group based on the data path allocated to the instruction sequence hierarchy graph.

摘要翻译： 编译装置包括指令序列层次图生成单元，其通过排列单位图来生成指示序列层次图，对于每一个，通过由一个指令序列中包含的多个微指令实现的数据路径被分配， 包括在目标处理器中的各个功能单元是节点，并且功能单元之间的数据线是边缘，以对应于多个指令序列的执行顺序，并且通过连接具有与硬件对应的边缘的排列的单位图 路径能够跨越指令序列建立数据路径; 数据路径分配单元，其向构成指令序列层次图的每个单位图分配数据路径; 以及对象程序输出单元，其基于分配给指令序列层次图的数据路径生成指令序列组。

公开(公告)号：US20100110213A1

公开(公告)日：2010-05-06

申请号：US12552680

申请日：2009-09-02

申请人： Katsuyuki KIMURA ,  Takashi MIYAMORI ,  Shunichi ISHIWATA ,  Takahisa WADA ,  Keiri NAKANISHI ,  Masato SUMIYOSHI ,  Yasuki TANABE ,  Ryuji HADA

发明人： Katsuyuki KIMURA ,  Takashi MIYAMORI ,  Shunichi ISHIWATA ,  Takahisa WADA ,  Keiri NAKANISHI ,  Masato SUMIYOSHI ,  Yasuki TANABE ,  Ryuji HADA

IPC分类号： H04N5/225 ,  G06T1/00

CPC分类号： G06T1/60 ,  H04N1/00931 ,  H04N1/2137 ,  H04N2101/00 ,  H04N2201/3287 ,  H04N2201/3292

摘要： An input unit that sequentially writes a digital image signal to be input in a first buffer while counting number of pixels of the digital image signal, and that writes the written digital image signal in a second buffer; and a command fetching/issuing unit that calculates a position of a pixel based on process delay information that is added to an image processing command and that indicates a delay amount required until image processing by the command is started since the input of the digital image signal, and a counter value indicating the number of pixels, and that issues the image processing command when the position of the pixel is in a valid area are included. Image processing is performed on pixels written in the second buffer based on the issued image processing command.

摘要翻译： 一种输入单元，其在计数所述数字图像信号的像素数量的同时，顺序地写入要输入的第一缓冲器的数字图像信号，并将所述写入的数字图像信号写入第二缓冲器; 以及命令获取/发布单元，其基于加到图像处理命令的处理延迟信息来计算像素的位置，并且指示由命令进行的图像处理之前所需的延迟量，从数字图像信号的输入开始 以及指示像素数的计数器值，并且当像素的位置在有效区域时发出图像处理命令。 基于发出的图像处理命令对写入第二缓冲器的像素进行图像处理。

公开(公告)号：US20100103282A1

公开(公告)日：2010-04-29

申请号：US12512593

申请日：2009-07-30

申请人： Keiri NAKANISHI ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Masato Sumiyoshi ,  Yasuki Tanabe ,  Ryuji Hada

发明人： Keiri NAKANISHI ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Masato Sumiyoshi ,  Yasuki Tanabe ,  Ryuji Hada

IPC分类号： H04N5/76

CPC分类号： H04N5/77 ,  G06F9/30043 ,  G06F9/35 ,  G06F9/355

摘要： An image processing apparatus has: a data memory configured to store image data; an RP register configured to hold a two-dimensional address indicating a position of an RP in a frame of image data; and an RP control section configured to control the two-dimensional address held by the RP register on the basis of the width and height of the frame. Furthermore, the image processing apparatus has an address calculation unit configured to, when reading target pixel data is read from the data memory on the basis of an instruction code provided with a field for specifying a two-dimensional relative position from the RP by a combination of two immediate values, calculate an address at which the reading target pixel data is stored, on the basis of the two-dimensional address, the combination of immediate values and the width of the frame.

摘要翻译： 图像处理装置具有：数据存储器，被配置为存储图像数据; RP寄存器，被配置为保存指示图像数据的帧中的RP的位置的二维地址; 以及RP控制部，被配置为基于帧的宽度和高度来控制由RP寄存器保持的二维地址。 此外，图像处理装置具有地址计算单元，其被配置为当基于具有用于通过组合从RP指定二维相对位置的字段的指令代码从数据存储器读取目标像素数据时， 基于二维地址，立即值的组合和帧的宽度，计算存储读取目标像素数据的地址。

公开(公告)号：US20100005271A1

公开(公告)日：2010-01-07

申请号：US12482876

申请日：2009-06-11

申请人： Takahisa WADA ,  Katsuyuki Kimura ,  Shunichi Ishiwata ,  Takashi Miyamori ,  Ryuji Hada ,  Keiri Nakanishi ,  Yasuki Tanabe ,  Masato Sumiyoshi

发明人： Takahisa WADA ,  Katsuyuki Kimura ,  Shunichi Ishiwata ,  Takashi Miyamori ,  Ryuji Hada ,  Keiri Nakanishi ,  Yasuki Tanabe ,  Masato Sumiyoshi

IPC分类号： G06F12/06 ,  G06F9/38

CPC分类号： G06F9/342 ,  G06F12/1441

摘要： A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an address of a first memory region by the processor is matched with the write-data requested to be written into the address of the second memory region, and if the read-data is matched with the write-data, prevents the write-data from being written into the address of the second memory region.

摘要翻译： 存储器控制器在接收到将写入数据写入由处理器发出的第二存储器区域的地址的写入请求时，确定由处理器请求从第一存储器区域的地址请求的读取数据是否与 写入数据被请求写入第二存储器区域的地址，并且如果读取数据与写入数据匹配，则防止将写入数据写入第二存储器区域的地址。

公开(公告)号：US07617420B2

公开(公告)日：2009-11-10

申请号：US11148330

申请日：2005-06-09

申请人： Katsuyuki Kimura

发明人： Katsuyuki Kimura

IPC分类号： G06F11/00

CPC分类号： G06F11/3636

摘要： A trace analyzing apparatus, which includes a trace analysis table, an instruction reconstruction unit that reconstructs and sends an execution address and an instruction code of trace information, and an object code list storage unit, reads out an object code list and trace information, captures each piece of information in reverse order from the last stored address information stored in an address register, and then registers them in the trace analysis table.

摘要翻译： 一种跟踪分析装置，其包括跟踪分析表，重建并发送执行地址的指令重建单元和跟踪信息的指令代码以及目标代码列表存储单元，读取目标代码列表和跟踪信息，捕获 每条信息从存储在地址寄存器中的最后存储的地址信息的顺序相反，然后将其注册到跟踪分析表中。