Thin film transistor with self-aligned intra-gate electrode
    1.
    发明申请
    Thin film transistor with self-aligned intra-gate electrode 失效
    具有自对准栅极间电极的薄膜晶体管

    公开(公告)号:US20050056838A1

    公开(公告)日:2005-03-17

    申请号:US10869210

    申请日:2004-06-16

    摘要: A thin film transistor for use in an active matrix liquid crystal display includes a substrate, a source and a drain regions, and at least a gate electrode. The substrate includes therein a plurality of intrinsic regions, at least one first doped region and two second doped regions. The first doped region is disposed between the plurality of intrinsic regions. The plurality of intrinsic regions are linked together to form a connection structure via the first doped region, and the two second doped regions are disposed at both ends of the connection structure, respectively. The source and the drain regions are coupled to the two second doped regions disposed at both ends of the connection structure, respectively. The gate electrode is disposed over the plurality of intrinsic regions, such that the periphery of each of the plurality of intrinsic regions and the periphery of a corresponding gate electrode are substantially aligned with each other.

    摘要翻译: 用于有源矩阵液晶显示器的薄膜晶体管包括衬底,源极和漏极区以及至少栅电极。 衬底中包括多个本征区域,至少一个第一掺杂区域和两个第二掺杂区域。 第一掺杂区域设置在多个固有区域之间。 多个本征区域连接在一起,以经由第一掺杂区域形成连接结构,并且两个第二掺杂区域分别设置在连接结构的两端。 源区和漏区分别耦合到设置在连接结构两端的两个第二掺杂区。 栅电极设置在多个本征区域上,使得多个本征区域中的每一个的周边和相应的栅电极的周边基本上彼此对准。

    Thin film transistor with self-aligned intra-gate electrode
    2.
    发明授权
    Thin film transistor with self-aligned intra-gate electrode 失效
    具有自对准栅极间电极的薄膜晶体管

    公开(公告)号:US07009204B2

    公开(公告)日:2006-03-07

    申请号:US10869210

    申请日:2004-06-16

    IPC分类号: H01L29/04

    摘要: A thin film transistor for use in an active matrix liquid crystal display includes a substrate, a source and a drain regions, and at least a gate electrode. The substrate includes therein a plurality of intrinsic regions, at least one first doped region and two second doped regions. The first doped region is disposed between the plurality of intrinsic regions. The plurality of intrinsic regions are linked together to form a connection structure via the first doped region, and the two second doped regions are disposed at both ends of the connection structure, respectively. The source and the drain regions are coupled to the two second doped regions disposed at both ends of the connection structure, respectively. The gate electrode is disposed over the plurality of intrinsic regions, such that the periphery of each of the plurality of intrinsic regions and the periphery of a corresponding gate electrode are substantially aligned with each other.

    摘要翻译: 用于有源矩阵液晶显示器的薄膜晶体管包括衬底,源极和漏极区以及至少栅电极。 衬底中包括多个本征区域,至少一个第一掺杂区域和两个第二掺杂区域。 第一掺杂区域设置在多个固有区域之间。 多个本征区域连接在一起,以经由第一掺杂区域形成连接结构,并且两个第二掺杂区域分别设置在连接结构的两端。 源区和漏区分别耦合到设置在连接结构两端的两个第二掺杂区。 栅电极设置在多个本征区域上,使得多个本征区域中的每一个的周边和相应的栅电极的周边基本上彼此对准。