公开(公告)号：US5866448A

公开(公告)日：1999-02-02

申请号：US902757

申请日：1997-07-30

申请人： Yelehanka Ramachandramurthy Pradeep ,  Tang Kok Hiang ,  Mei Sheng Zhou

发明人： Yelehanka Ramachandramurthy Pradeep ,  Tang Kok Hiang ,  Mei Sheng Zhou

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/823814 ,  Y10S438/963

摘要： A method for fabrication of a lightly-doped-drain (LDD) structure for self aligned polysilicon gate MOSFETs is described wherein a polymer layer, formed along the sidewall during the patterning process of the polysilicon gate electrode, is used to mask the source/drain ion implant. The sidewall polymer layer replaces the conventional silicon oxide sidewall as an LDD spacer and offers improved thickness control as well as an improved sequence of processing steps whereby the deposition of a spacer oxide layer onto the gate oxide is eliminated. A cap oxide layer first deposited over the gate polysilicon layer. This oxide layer is then patterned and etched using RIE under conditions which form a polymer sidewall layer along the edges of the cap oxide pattern. The polysilicon layer is then etched, and has a pattern concentric with the cap oxide pattern but wider by the thickness of the polymer sidewall. After removal of the polymer and residual photoresist, the source/drain implant is performed, followed by removal of the polysilicon lip by RIE using the cap oxide as a mask. The LDD implant is then performed.

摘要翻译： 描述了一种制造用于自对准多晶硅栅极MOSFET的轻掺杂漏极（LDD）结构的方法，其中在多晶硅栅电极的图案化工艺期间沿侧壁形成的聚合物层用于掩蔽源/漏 离子植入。 侧壁聚合物层代替常规的氧化硅侧壁作为LDD间隔物，并提供改进的厚度控制以及改进的处理步骤顺序，从而消除间隔氧化物层沉积到栅极氧化物上。 首先沉积在栅极多晶硅层上的覆盖氧化物层。 然后使用RIE在沿着氧化物图案的边缘形成聚合物侧壁层的条件下对该氧化物层进行构图和蚀刻。 然后蚀刻多晶硅层，并且具有与盖氧化物图案同心的图案，但是通过聚合物侧壁的厚度更宽。 在去除聚合物和残余光致抗蚀剂之后，进行源极/漏极注入，随后通过RIE使用帽氧化物作为掩模去除多晶硅唇缘。 然后执行LDD植入。

公开(公告)号：US07439084B2

公开(公告)日：2008-10-21

申请号：US11405650

申请日：2006-04-17

申请人： Tang Kok Hiang ,  Ming-Ta Lei

发明人： Tang Kok Hiang ,  Ming-Ta Lei

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： H01L22/14 ,  G01R31/307

摘要： A method for determining leakage currents in integrated circuits is provided. The method includes providing a substrate comprising a target structure having a first region and a second region, grounding the second region, scanning the substrate using a scanning electron microscope to produce a voltage contrast (VC) image, determining a gray level of the first region in the VC image, and using the gray level to determine a leakage current between the first region and the second region.

摘要翻译： 提供了一种用于确定集成电路中的漏电流的方法。 该方法包括提供包括具有第一区域和第二区域的目标结构的基板，使第二区域接地，使用扫描电子显微镜扫描基板以产生电压对比度（VC）图像，确定第一区域的灰度级 在VC图像中，并且使用灰度级来确定第一区域和第二区域之间的漏电流。