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1.发明授权AC coupling circuit integrated with receiver with hybrid stable common-mode voltage generation and baseline wander compensation 失效交流耦合电路与接收器集成，具有混合稳定的共模电压产生和基线漂移补偿公开(公告)号：US07961817B2
公开(公告)日：2011-06-14
申请号：US11634671
申请日：2006-12-06
CPC分类号： H04L25/0276 , H04L25/06
摘要： In a receiver, an AC-coupling solution uses a fully integrated circuit for simultaneously providing both baseline wander compensation and common-mode voltage generation. Usefully, an integrated capacitor is placed between the receiver input pin and the input buffer, and a high resistive impedance element is connected to the internal high-speed data node after the capacitor. An on-chip voltage generation and correction circuit is connected to the other side of the impedance element to generate a common-mode voltage, and to provide dynamic, fine adjustment for the received data voltage level. The voltage correction circuit is controlled by the feedback of data detected by the clock and data recovery unit (CDRU) of the receiver. The feedback data passes through a weighting element, wherein the amount of feedback gain is adjustable to provide a summing weight and thereby achieve a desired BLW compensation. Register bits are used to control an on-chip reference voltage generator that consists of a resistor ladder to generate the reference voltage.
摘要翻译： 在接收机中，AC耦合解决方案使用完全集成电路，同时提供基线漂移补偿和共模电压生成。 有用的是，在接收器输入引脚和输入缓冲器之间放置一个集成的电容器，并且高电阻阻抗元件连接到电容器之后的内部高速数据节点。 片上电压产生和校正电路连接到阻抗元件的另一侧以产生共模电压，并为接收的数据电压电平提供动态的微调。 电压校正电路由接收机的时钟和数据恢复单元（CDRU）检测到的数据的反馈来控制。 反馈数据通过加权元件，其中反馈增益的量可调，以提供求和权重，从而实现所需的BLW补偿。 寄存器位用于控制片上参考电压发生器，该发生器由电阻梯形成，用于产生参考电压。
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2.发明申请AC coupling circuit integrated with receiver with hybrid stable common-mode voltage generation and baseline-wander compensation 失效交流耦合电路与接收器集成，具有混合稳定的共模电压产生和基线漂移补偿公开(公告)号：US20080063091A1
公开(公告)日：2008-03-13
申请号：US11634671
申请日：2006-12-06
IPC分类号： H04L25/00
CPC分类号： H04L25/0276 , H04L25/06
摘要： In a receiver, an AC-coupling solution uses a fully integrated circuit for simultaneously providing both baseline wander compensation and common-mode voltage generation. Usefully, an integrated capacitor is placed between the receiver input pin and the input buffer, and a high resistive impedance element is connected to the internal high-speed data node after the capacitor. An on-chip voltage generation and correction circuit is connected to the other side of the impedance element to generate a common-mode voltage, and to provide dynamic, fine adjustment for the received data voltage level. The voltage correction circuit is controlled by the feedback of data detected by the clock and data recovery unit (CDRU) of the receiver. The feedback data passes through a weighting element, wherein the amount of feedback gain is adjustable to provide a summing weight and thereby achieve a desired BLW compensation. Register bits are used to control an on-chip reference voltage generator that consists of a resistor ladder to generate the reference voltage.
摘要翻译： 在接收机中，AC耦合解决方案使用完全集成电路，同时提供基线漂移补偿和共模电压生成。 有用的是，在接收器输入引脚和输入缓冲器之间放置一个集成的电容器，并且高电阻阻抗元件连接到电容器之后的内部高速数据节点。 片上电压产生和校正电路连接到阻抗元件的另一侧以产生共模电压，并为接收的数据电压电平提供动态的微调。 电压校正电路由接收机的时钟和数据恢复单元（CDRU）检测到的数据的反馈来控制。 反馈数据通过加权元件，其中反馈增益的量可调，以提供求和权重，从而实现所需的BLW补偿。 寄存器位用于控制片上参考电压发生器，该发生器由电阻梯形成，用于产生参考电压。
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3.发明授权公开(公告)号：US09014252B2
公开(公告)日：2015-04-21
申请号：US11634645
申请日：2006-12-06
CPC分类号： H04L25/03178 , H04L25/03057 , H04L2025/03356
摘要： A channel equalization scheme is provided. A linear equalizer using a continuous-time linear equalization and a decision feedback equalizer using a discrete-time decision feedback equalization are integrated together from a hybrid receiver equalizer. The continuous-time linear equalization scheme and the discrete-time decision feedback equalization scheme are blended using a joint adaptation algorithm to form an equalization scheme for inter-symbol interference cancellation in the hybrid receiver equalizer. The hybrid receiver equalizer controls crosstalk while maintaining signal bandwidth and linearity of a signal by the high-order high frequency roll-off of the linear equalizer used. Using this configuration, the hybrid receiver equalizer eliminates the need for adaptive bandwidth controller used in conventional low-pass receiver equalization schemes. The hybrid receiver equalizer can be used in receivers for dual-speed simultaneous transmission on the same physical link. The hybrid receiver equalizer can also be used in receivers for simultaneous forward and back-channel transmission using differential-signaling in multi-Gbps transceivers.
摘要翻译： 提供了一种信道均衡方案。 使用连续时间线性均衡的线性均衡器和使用离散时间判决反馈均衡的判决反馈均衡器从混合接收机均衡器集成在一起。 使用联合自适应算法来混合连续时间线性均衡方案和离散时间决策反馈均衡方案，以在混合接收机均衡器中形成符号间干扰消除的均衡方案。 混合接收机均衡器控制串扰，同时通过所使用的线性均衡器的高阶高频滚降来维持信号的信号带宽和线性度。 使用这种配置，混合接收机均衡器消除了对传统低通接收机均衡方案中使用的自适应带宽控制器的需要。 混合接收均衡器可用于同一物理链路上双速同时传输的接收机。 混合接收机均衡器也可以用于接收机，用于使用多Gbps收发器中的差分信号进行同步正向和反向信道传输。
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4.发明申请公开(公告)号：US20080069191A1
公开(公告)日：2008-03-20
申请号：US11634645
申请日：2006-12-06
CPC分类号： H04L25/03178 , H04L25/03057 , H04L2025/03356
摘要： A system and a method for channel equalization are provided. A linear equalizer using a continuous-time linear equalization and a decision feedback equalizer using a discrete-time decision feedback equalization are integrated together from a hybrid receiver equalizer. The continuous-time linear equalization scheme and the discrete-time decision feedback equalization scheme are blended using a joint adaptation algorithm to form an equalization scheme for inter-symbol interference cancellation in the hybrid receiver equalizer. The hybrid receiver equalizer controls crosstalk while maintaining signal bandwidth and linearity of a signal by the high-order high frequency roll-off of the linear equalizer used. Using this configuration, the hybrid receiver equalizer eliminates the need for adaptive bandwidth controller used in conventional low-pass receiver equalization schemes. The hybrid receiver equalizer can be used in receivers for dual-speed simultaneous transmission on the same physical link. The hybrid receiver equalizer can also be used in receivers for simultaneous forward and back-channel transmission using differential-signaling in multi-Gbps transceivers.
摘要翻译： 提供了一种用于信道均衡的系统和方法。 使用连续时间线性均衡的线性均衡器和使用离散时间判决反馈均衡的判决反馈均衡器从混合接收机均衡器集成在一起。 使用联合自适应算法来混合连续时间线性均衡方案和离散时间决策反馈均衡方案，以在混合接收机均衡器中形成符号间干扰消除的均衡方案。 混合接收机均衡器控制串扰，同时通过所使用的线性均衡器的高阶高频滚降来维持信号的信号带宽和线性度。 使用这种配置，混合接收机均衡器消除了对传统低通接收机均衡方案中使用的自适应带宽控制器的需要。 混合接收均衡器可用于同一物理链路上双速同时传输的接收机。 混合接收机均衡器也可以用于接收机，用于使用多Gbps收发器中的差分信号进行同步正向和反向信道传输。
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公开(公告)号：US07825522B2
公开(公告)日：2010-11-02
申请号：US11741195
申请日：2007-04-27
IPC分类号： H01L23/48 , H01L27/108
CPC分类号： H01G4/228 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding and (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer.
摘要翻译： 公开了一种在芯片上制造的器件。 该装置通常包括（A）在芯片的中间导电层中产生的第一图案和第二图案，（B）在中间导电层上方的绝缘层中形成的至少一个通孔，（C）产生的第一凸起 在绝缘层上方的顶部导电层中。 第一图案通常建立第一电容器的多个板中的第一个。 通孔可以与第二图案对准。 第一凸块可以（i）位于第一板的正上方，（ii）建立第一电容器的第二板，（iii）适于倒装芯片接合，以及（iv）通过 通过使得第一电容器的两个板可在中间导电层中接近。
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公开(公告)号：US08384226B2
公开(公告)日：2013-02-26
申请号：US12885722
申请日：2010-09-20
IPC分类号： H01L23/48 , H01L27/108 , H01L21/00
CPC分类号： H01G4/228 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding, (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer. The first pattern and the second pattern may be shaped as interlocking combs.
摘要翻译： 公开了一种在芯片上制造的器件。 该装置通常包括（A）在芯片的中间导电层中产生的第一图案和第二图案，（B）在中间导电层上方的绝缘层中形成的至少一个通孔，（C）产生的第一凸起 在绝缘层上方的顶部导电层中。 第一图案通常建立第一电容器的多个板中的第一个。 通孔可以与第二图案对准。 第一凸块可以（i）位于第一板的正上方，（ii）建立第一电容器的第二板，（iii）适于倒装芯片接合，（iv）通过 通过使得第一电容器的两个板可在中间导电层中接近。 第一图案和第二图案可以被成形为互锁梳。
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公开(公告)号：US20110006395A1
公开(公告)日：2011-01-13
申请号：US12885722
申请日：2010-09-20
CPC分类号： H01G4/228 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding, (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer. The first pattern and the second pattern may be shaped as interlocking combs.
摘要翻译： 公开了一种在芯片上制造的器件。 该装置通常包括（A）在芯片的中间导电层中产生的第一图案和第二图案，（B）在中间导电层上方的绝缘层中形成的至少一个通孔，（C）产生的第一凸起 在绝缘层上方的顶部导电层中。 第一图案通常建立第一电容器的多个板中的第一个。 通孔可以与第二图案对准。 第一凸块可以（i）位于第一板的正上方，（ii）建立第一电容器的第二板，（iii）适于倒装芯片接合，（iv）通过 通过使得第一电容器的两个板可在中间导电层中接近。 第一图案和第二图案可以被成形为互锁梳。
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