公开(公告)号：US08369154B2

公开(公告)日：2013-02-05

申请号：US12944711

申请日：2010-11-11

申请人： Ying-Je Chen ,  Yun-Jen Ting ,  Wein-Town Sun ,  Kai-Yuan Hsiao ,  Cheng-Jye Liu

发明人： Ying-Je Chen ,  Yun-Jen Ting ,  Wein-Town Sun ,  Kai-Yuan Hsiao ,  Cheng-Jye Liu

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/3468

摘要： A nonvolatile memory device for reducing programming current and improving reliability comprises a memory cell array, a write circuit, and a verification circuit. The memory cell array comprises memory cells arranged at crossing points of a bit-line and word-line matrix of the memory cell array. The write circuit provides multiple variable pulses to each word-line for programming. The multiple variable pulses have predetermined amplitude for keeping gate injection current roughly maximum while lowering conduction current during programming operation. The verification circuit senses variation of the conduction current during the programming operation, and disables the programming operation if the sensed conduction current during the programming operation reaches a predetermined value.

摘要翻译： 用于减少编程电流和提高可靠性的非易失性存储器件包括存储单元阵列，写入电路和验证电路。 存储单元阵列包括布置在存储单元阵列的位线和字线矩阵的交叉点处的存储单元。 写电路为每个字线提供多个可变脉冲进行编程。 多个可变脉冲具有预定的幅度，以在编程操作期间降低导通电流，保持栅极注入电流大致最大。 验证电路在编程操作期间感测导通电流的变化，并且如果在编程操作期间感测到的传导电流达到预定值，则禁止编程操作。

公开(公告)号：US20110235427A1

公开(公告)日：2011-09-29

申请号：US12944711

申请日：2010-11-11

申请人： Ying-Je Chen ,  Yun-Jen Ting ,  Wein-Town Sun ,  Kai-Yuan Hsiao ,  Cheng-Jye Liu

发明人： Ying-Je Chen ,  Yun-Jen Ting ,  Wein-Town Sun ,  Kai-Yuan Hsiao ,  Cheng-Jye Liu

IPC分类号： G11C16/12 ,  G11C16/26

CPC分类号： G11C16/10 ,  G11C16/3468

摘要： A nonvolatile memory device for reducing programming current and improving reliability comprises a memory cell array, a write circuit, and a verification circuit. The memory cell array comprises memory cells arranged at crossing points of a bit-line and word-line matrix of the memory cell array. The write circuit provides multiple variable pulses to each word-line for programming. The multiple variable pulses have predetermined amplitude for keeping gate injection current roughly maximum while lowering conduction current during programming operation. The verification circuit senses variation of the conduction current during the programming operation, and disables the programming operation if the sensed conduction current during the programming operation reaches a predetermined value.

摘要翻译： 用于减少编程电流和提高可靠性的非易失性存储器件包括存储单元阵列，写入电路和验证电路。 存储单元阵列包括布置在存储单元阵列的位线和字线矩阵的交叉点处的存储单元。 写电路为每个字线提供多个可变脉冲进行编程。 多个可变脉冲具有预定的幅度，以在编程操作期间降低导通电流，保持栅极注入电流大致最大。 验证电路在编程操作期间感测导通电流的变化，并且如果在编程操作期间感测到的传导电流达到预定值，则禁止编程操作。

公开(公告)号：US20130083598A1

公开(公告)日：2013-04-04

申请号：US13468043

申请日：2012-05-10

申请人： Kai-Yuan Hsiao ,  Wen-Yuan Lee ,  Yun-Jen Ting ,  Cheng-Jye Liu ,  Wein-Town Sun

发明人： Kai-Yuan Hsiao ,  Wen-Yuan Lee ,  Yun-Jen Ting ,  Cheng-Jye Liu ,  Wein-Town Sun

IPC分类号： G11C16/06

CPC分类号： G11C16/0466 ,  G11C14/00 ,  G11C14/0063 ,  G11C16/0416 ,  H01L27/11565 ,  H01L29/792

摘要： Each memory cell of a plurality of memory cells of a memory has a well, source and drain regions, a storage layer, and a gate. The memory cells are in a matrix. Same column drain regions connect to the same bit line, same row gates connect to the same word line, and same column source regions connect to the same source line. The memory is programmed by applying a first voltage to a word line electrically connected to a memory cell of the plurality of memory cells, applying a second voltage different from the first voltage by at least a programming threshold to a bit line electrically connected to the memory cell, applying a third voltage different from the first voltage by at least the programming threshold to a source line electrically connected to the memory cell, and applying a substrate voltage to the plurality of memory cells.

摘要翻译： 存储器的多个存储单元的每个存储单元具有阱，源极和漏极区，存储层和栅极。 存储单元是矩阵。 相同的列漏极区域连接到相同的位线，相同的行栅极连接到相同的字线，并且相同的列源区域连接到相同的源极线。 通过将第一电压施加到电连接到多个存储器单元的存储单元的字线来对存储器进行编程，将不同于第一电压的第二电压施加至少编程阈值至与存储器电连接的位线 将与所述第一电压不同的第三电压施加至所述编程阈值至与所述存储单元电连接的源极线，以及向所述多个存储单元施加衬底电压。

公开(公告)号：US08837219B2

公开(公告)日：2014-09-16

申请号：US13468043

申请日：2012-05-10

申请人： Kai-Yuan Hsiao ,  Wen-Yuan Lee ,  Yun-Jen Ting ,  Cheng-Jye Liu ,  Wein-Town Sun

发明人： Kai-Yuan Hsiao ,  Wen-Yuan Lee ,  Yun-Jen Ting ,  Cheng-Jye Liu ,  Wein-Town Sun

IPC分类号： G11C16/04 ,  G11C14/00 ,  H01L27/115 ,  H01L29/792

CPC分类号： G11C16/0466 ,  G11C14/00 ,  G11C14/0063 ,  G11C16/0416 ,  H01L27/11565 ,  H01L29/792

摘要： Each memory cell of a plurality of memory cells of a memory has a well, source and drain regions, a storage layer, and a gate. The memory cells are in a matrix. Same column drain regions connect to the same bit line, same row gates connect to the same word line, and same column source regions connect to the same source line. The memory is programmed by applying a first voltage to a word line electrically connected to a memory cell of the plurality of memory cells, applying a second voltage different from the first voltage by at least a programming threshold to a bit line electrically connected to the memory cell, applying a third voltage different from the first voltage by at least the programming threshold to a source line electrically connected to the memory cell, and applying a substrate voltage to the plurality of memory cells.

摘要翻译： 存储器的多个存储单元的每个存储单元具有阱，源极和漏极区，存储层和栅极。 存储单元是矩阵。 相同的列漏极区域连接到相同的位线，相同的行栅极连接到相同的字线，并且相同的列源区域连接到相同的源极线。 通过将第一电压施加到电连接到多个存储器单元的存储单元的字线来对存储器进行编程，将不同于第一电压的第二电压施加至少编程阈值至与存储器电连接的位线 将与所述第一电压不同的第三电压施加至所述编程阈值至与所述存储单元电连接的源极线，以及向所述多个存储单元施加衬底电压。

公开(公告)号：US08259504B2

公开(公告)日：2012-09-04

申请号：US12503821

申请日：2009-07-15

申请人： Yun-Jen Ting ,  Kai-Yuan Hsiao

发明人： Yun-Jen Ting ,  Kai-Yuan Hsiao

IPC分类号： G11C16/04

CPC分类号： G11C16/344 ,  G11C11/5628 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： Multi-stage pulses are used to program/erase the memory so as to reduce the slow program/erase bit issue. A first predetermined voltage bias is applied to a memory cell for a predetermined number of times. Each time the voltage bias is applied to the memory cell the memory is verified against a criterion. If the verification failed after the predetermined number of times applying the first predetermined voltage bias, a second predetermined voltage bias is applied to program/erase the nonvolatile memory. If the verification failed after applying the second predetermined voltage bias, a third predetermined voltage bias is applied to program/erase the nonvolatile memory.

摘要翻译： 多级脉冲用于对存储器进行编程/擦除，以减少缓慢的编程/擦除位问题。 将第一预定电压偏压施加到存储器单元预定次数。 每当将电压偏压施加到存储器单元时，根据标准验证存储器。 如果在预定次数施加第一预定电压偏置之后验证失败，则施加第二预定电压偏置来对非易失性存储器进行编程/擦除。 如果在施加第二预定电压偏置之后验证失败，则施加第三预定电压偏置来对非易失性存储器进行编程/擦除。

公开(公告)号：US20110013459A1

公开(公告)日：2011-01-20

申请号：US12503821

申请日：2009-07-15

申请人： Yun-Jen Ting ,  Kai-Yuan Hsiao

发明人： Yun-Jen Ting ,  Kai-Yuan Hsiao

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/344 ,  G11C11/5628 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： A method for programming/erasing a nonvolatile memory uses the multi-stage pulses to program/erase the memory so as to reduce the slow program/erase bit issue. The method applies a first predetermined voltage bias to a memory cell for a predetermined number of times. Each time the voltage bias is applied to the memory cell the memory is verified against a criterion. If the verification failed after the predetermined number of times applying the first predetermined voltage bias, a second predetermined voltage bias is applied to program/erase the nonvolatile memory. If the verification failed after applying the second predetermined voltage bias, a third predetermined voltage bias is applied to program/erase the nonvolatile memory.

摘要翻译： 用于编程/擦除非易失性存储器的方法使用多级脉冲对存储器进行编程/擦除，以减少缓慢的编程/擦除位问题。 该方法对存储器单元施加预定次数的第一预定电压偏置。 每当将电压偏压施加到存储器单元时，根据标准验证存储器。 如果在预定次数施加第一预定电压偏置之后验证失败，则施加第二预定电压偏置来对非易失性存储器进行编程/擦除。 如果在施加第二预定电压偏置之后验证失败，则施加第三预定电压偏置来对非易失性存储器进行编程/擦除。