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    AND circuit
    4.
    发明授权
    AND circuit 有权
    AND电路

    公开(公告)号：US07205796B2

    公开(公告)日：2007-04-17

    申请号：US11045475

    申请日：2005-01-31

    Applicant: Yoichi Kawano

    Inventor： Yoichi Kawano

    IPC: H03K19/20

    CPC classification number: H03K19/09432

    Abstract: An AND circuit is provided, which has a first differential pair including a first transistor and a second transistor, to which a first input differential signal is inputted, a second differential pair including a third transistor and a fourth transistor, to which a fixed bias is inputted, a third differential pair including a fifth transistor and a sixth transistor, to which a second input differential signal is inputted, and in which the first differential pair is connected to the fifth transistor and the second differential pair is connected to the sixth transistor, and an output terminal, which is connected to the first or second transistor and outputs an AND signal or a NAND signal of the first and second input differential signals.

    Abstract translation: 提供AND电路，其具有包括第一晶体管和第二晶体管的第一差分对，输入第一输入差分信号;第二差分对，包括第三晶体管和第四晶体管，固定偏置为 输入第三差分对，包括第五晶体管和第六晶体管，输入第二输入差分信号，并且其中第一差分对连接到第五晶体管，第二差分对连接到第六晶体管， 以及输出端子，其连接到第一或第二晶体管，并输出第一和第二输入差分信号的“与”信号或“与非”信号。

    Differential amplifier circuit
    6.
    发明授权
    Differential amplifier circuit 有权
    差分放大电路

    公开(公告)号：US08461926B2

    公开(公告)日：2013-06-11

    申请号：US13309687

    申请日：2011-12-02

    Applicant: Akiko Mineyama ,  Yoichi Kawano ,  Toshihide Suzuki

    Inventor： Akiko Mineyama ,  Yoichi Kawano ,  Toshihide Suzuki

    IPC: H03F3/45

    CPC classification number: H03F3/45179 ,  H03F1/56 ,  H03F2200/102 ,  H03F2200/387 ,  H03F2203/45318 ,  H03F2203/45332 ,  H03F2203/45654 ,  H03F2203/45688

    Abstract: A differential amplifier circuit includes a first/second field effect transistor including a gate coupled to a first/second differential input signal terminal, a source coupled to a reference potential node, and a drain coupled to a first/second differential output signal terminal, a first variable capacitor coupled between the gate of the first field effect transistor and the drain of the second field effect transistor, a second variable capacitor coupled between the gate of the second field effect transistor and the drain of the first field effect transistor, and a first envelope detector configured to detect an envelope of a signal at the first differential output signal terminal or the second differential output signal terminal, the first variable capacitor and/or the second variable capacitor has a capacitance that varies in accordance with an envelope detected by the first envelope detector.

    Abstract translation: 差分放大器电路包括第一/第二场效应晶体管，其包括耦合到第一/第二差分输入信号端子的栅极，耦合到参考电势节点的源极和耦合到第一/第二差分输出信号端子的漏极， 耦合在第一场效应晶体管的栅极和第二场效应晶体管的漏极之间的第一可变电容器，耦合在第二场效应晶体管的栅极和第一场效应晶体管的漏极之间的第二可变电容器， 包络检测器被配置为检测第一差分输出信号端或第二差分输出信号端的信号包络，第一可变电容和/或第二可变电容具有根据由第一差分输出信号 包络检测器。

    Transmitter circuit and radio transmission apparatus for transmitting data via radio by using impulses
    8.
    发明授权
    Transmitter circuit and radio transmission apparatus for transmitting data via radio by using impulses 有权
    用于通过使用脉冲通过无线电发送数据的发送器电路和无线电发送装置

    公开(公告)号：US08054908B2

    公开(公告)日：2011-11-08

    申请号：US11987703

    申请日：2007-12-04

    Applicant: Yasuhiro Nakasha ,  Yoichi Kawano

    Inventor： Yasuhiro Nakasha ,  Yoichi Kawano

    IPC: H04L27/00

    CPC classification number: H04L27/04 ,  H04B1/71635 ,  H04B1/7172 ,  H04B1/7174 ,  H04L25/4902

    Abstract: A transmitter circuit, which transmits data by using an impulse, has a variable delay circuit and a logic circuit. The variable delay circuit takes a clock as an input, and delays the clock in accordance with the data. The logic circuit takes the clock and an output of the variable delay circuit as inputs, and outputs an impulse by performing a logic operation between the clock and the output of the variable delay circuit.

    Abstract translation: 通过使用脉冲发送数据的发送器电路具有可变延迟电路和逻辑电路。 可变延迟电路采用时钟作为输入，并根据数据延迟时钟。 逻辑电路将时钟和可变延迟电路的输出作为输入，并通过在时钟和可变延迟电路的输出之间执行逻辑运算来输出脉冲。

    Radar device and processing method of the same
    9.
    发明授权
    Radar device and processing method of the same 有权
    雷达设备及其加工方法相同

    公开(公告)号：US07612709B2

    公开(公告)日：2009-11-03

    申请号：US12175081

    申请日：2008-07-17

    Applicant: Yoichi Kawano ,  Yasuhiro Nakasha

    Inventor： Yoichi Kawano ,  Yasuhiro Nakasha

    IPC: G01S13/08

    CPC classification number: G01S13/10 ,  G01S7/282

    Abstract: A radar device has a clock generator (131) generating a base clock; a transmitter (121 to 125) transmitting transmission pulses as gradually increasing a displacement amount with respect to each edge of the base clock; and a receiver (101 to 106) receiving reflected waves of the transmitted transmission pulses in synchronization with the edges of the base clock.

    Abstract translation: 雷达装置具有产生基准时钟的时钟发生器（131） 发送器（121至125），其相对于所述基本时钟的每个边缘逐渐增加位移量，发送发送脉冲; 以及与基准时钟的边沿同步地接收所发送的发送脉冲的反射波的接收器（101至106）。

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