公开(公告)号：US5153459A

公开(公告)日：1992-10-06

申请号：US206824

申请日：1988-06-15

申请人： Yong E. Park ,  Soo I. Cho ,  Dong S. Jun ,  Seung M. Seo

发明人： Yong E. Park ,  Soo I. Cho ,  Dong S. Jun ,  Seung M. Seo

IPC分类号： G11C11/4093 ,  G11C11/409 ,  G11C11/4096

CPC分类号： G11C11/4096 ,  G11C11/409

摘要： An improved data transmission circuit for complementary metal oxide semiconductor (CMOS) dynamic random access memory devices having a data input buffer for converting transistor-transistor logic (TTL) input data signals to CMOS logic level true and complement data signals is described. The data transmission circuit includes a pair of transmission gates for transferring the true and complement data signals in a write cycle, a pair of inverting stages connected between respective ones of the transmission gates and true and complement input/output (I/O) bus lines for inverting data signals from the transmission gates to provide the inverted data signals to true and complement I/O bus lines in the write cycle and an equalizing stage for precharging and equalizing true and complement I/O bus lines in a precharge cycle. The data transmission circuit is characterized in that each of the inverting stages can operate under the control of a block selecting clock signal regardless of the precharging voltages of the true and complement I/O bus lines.

摘要翻译： 描述了一种用于互补金属氧化物半导体（CMOS）动态随机存取存储器件的改进的数据传输电路，其具有用于将晶体管晶体管逻辑（TTL）输入数据信号转换为CMOS逻辑电平真实和补码数据信号的数据输入缓冲器。 数据传输电路包括一对传输门，用于在写入周期内传送真实和补码数据信号，连接在相应传输门之间的一对反相级和真和补输入/输出（I / O）总线 用于反转来自传输门的数据信号，以便在写入周期中将反相数据信号提供给真实和补码I / O总线，以及用于在预充电周期中对真和互补I / O总线进行预充电和均衡的均衡级。 数据传输电路的特征在于，不管真和互补I / O总线的预充电电压如何，每个反相级可在块选择时钟信号的控制下工作。

公开(公告)号：US4825417A

公开(公告)日：1989-04-25

申请号：US125389

申请日：1987-11-25

申请人： Seung M. Seo

发明人： Seung M. Seo

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00 ,  G11C11/24

CPC分类号： G11C11/4091 ,  G11C7/065 ,  H01L27/10805

摘要： A sense amplifier having an optimized structural lay-out for D-RAM on the C-MOS provides the same time lag from nodes of the sense amplifier and does not produce unbalances in the voltages. This allows the sense amplifier to uniformly distribute the parasitic capacitance of the bit lines used for the D-RAM on the C-MOS. The sense amplifier is connected to a memory cell array so that transistors and capacitors are coupled with a plurality of bit lines and word lines situated on the semiconductor substrate. The amplifier has a first semiconductor region which is within an N type well region located on the P type semiconductor substrate to form a first latch circuit. A second semiconductor region which is contiguous to the N type well region is also formed on the semiconductor substrate to form an N-MOS transistor. Lastly, a third semiconductor region, which is contiguous to the N type well region and the second semiconductor region, forms a second latch circuit having an N-MOS transistor. Thus, the sense amplifier is formed at a gate of the N-MOS transistor so that a transfer from the gate of N-MOS transistor through openings in the substrate caused by voltage differences produced by the charge distribution and storage capacitor of bit lines during an active cycle does not have a time lag.

摘要翻译： 在C-MOS上具有用于D-RAM的优化结构布局的读出放大器提供与读出放大器的节点相同的时滞，并且不会在电压中产生不平衡。 这允许读出放大器均匀地分配用于D-RAM的位线的寄生电容在C-MOS上。 读出放大器连接到存储单元阵列，使得晶体管和电容器与位于半导体衬底上的多个位线和字线耦合。 放大器具有位于P型半导体衬底上的N型阱区内的第一半导体区，以形成第一锁存电路。 在半导体衬底上也形成与N型阱区相邻的第二半导体区，形成N-MOS晶体管。 最后，与N型阱区域和第二半导体区域邻接的第三半导体区域形成具有N-MOS晶体管的第二锁存电路。 因此，读出放大器形成在N-MOS晶体管的栅极处，使得由N-MOS晶体管的栅极通过由位线的电荷分配和存储电容器产生的电压导致的衬底中的开口的转移 活动周期没有时间滞后。