利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

14 条记录 (耗时 0.016 秒)

    Sealing ring structure of a cosmetic container
    1.
    发明授权
    Sealing ring structure of a cosmetic container 有权
    化妆品容器的密封圈结构

    公开(公告)号：US08789540B2

    公开(公告)日：2014-07-29

    申请号：US13635641

    申请日：2010-10-28

    申请人： Yong Jun Lee ,  Jeen Gee Kim

    发明人： Yong Jun Lee ,  Jeen Gee Kim

    IPC分类号： A45D33/00 ,  A45D33/24 ,  B65D69/00 ,  B65D71/00 ,  B65D43/26 ,  B65D53/00 ,  A45D40/22

    CPC分类号： A45D33/003 ,  A45C13/008 ,  A45C13/1084 ,  A45D33/00 ,  A45D33/006 ,  A45D40/0068 ,  A45D40/222 ,  A45D2200/051 ,  Y10S206/823

    摘要： The present invention provides a novel structure for sealing a cosmetic container using a double-injection molded rib on the container body sealing against a deformable hard-rubber ring on the container cover. The invention will maximize product reliability by improving the sealing structure of a make-up base or cosmetic container through providing a clear, air-tight effect since the sealing structure cannot be deformed, even in the case of long-term use. The invention provides uniform, airtight adhesion without unequal distribution of coupling intensity between internal sealing components when the container cover is closed. Further, the aesthetics of the container are increased because a closure clasp is not necessary, and it is possible to eliminate the problem of dried-out product created when the container is fitted with a closure clasp or similar device.

    摘要翻译： 本发明提供一种用于在容器主体上密封化妆品容器的新型结构，该化妆品容器使用双重注射成型的肋密封在容器盖上的可变形的硬橡胶环上。 本发明通过提供透明的气密效果，即使在长期使用的情况下也不会发生变形，因此通过改善补充基底或化妆品容器的密封结构来最大限度地提高产品的可靠性。 当容器盖关闭时，本发明提供均匀的气密粘合性，而内部密封部件之间的耦合强度分布不均匀。 此外，由于不需要闭合扣，容器的美观性增加，并且可以消除当容器装配有闭合扣或类似装置时产生的干燥产品的问题。

    Method of manufacturing non-volatile memory device
    2.
    发明授权
    Method of manufacturing non-volatile memory device 失效
    制造非易失性存储器件的方法

    公开(公告)号：US07608505B2

    公开(公告)日：2009-10-27

    申请号：US11643880

    申请日：2006-12-22

    申请人： Yong Jun Lee

    发明人： Yong Jun Lee

    IPC分类号： H01L21/8247

    CPC分类号： H01L21/28282 ,  H01L29/4234 ,  H01L29/792

    摘要： A method of manufacturing a non-volatile memory device includes the steps of: defining an active region on a semiconductor substrate; forming a charge storage layer on the active region; forming a first conductive pattern on the charge storage layer, wherein the first conductive pattern has a bottom portion larger in width than a top portion thereof, the first conductive pattern further having a sloping sidewall connecting the top and bottom portions; forming an oxide layer on the sidewall of the first conductive pattern; forming a conformal second conductive layer on the first conductive pattern and on the active region around the first conductive pattern; and patterning the first conductive pattern and the second conductive layer to form a pair of first electrodes and a pair of second electrodes, respectively.

    摘要翻译： 制造非易失性存储器件的方法包括以下步骤：在半导体衬底上限定有源区; 在有源区上形成电荷存储层; 在所述电荷存储层上形成第一导电图案，其中所述第一导电图案具有宽度大于其顶部的底部，所述第一导电图案还具有连接所述顶部和底部的倾斜侧壁; 在第一导电图案的侧壁上形成氧化物层; 在所述第一导电图案上以及围绕所述第一导电图案的所述有源区上形成保形第二导电层; 以及图案化所述第一导电图案和所述第二导电层，以分别形成一对第一电极和一对第二电极。

    Method of manufacturing split gate type non-volatile memory device
    3.
    发明授权
    Method of manufacturing split gate type non-volatile memory device 有权
    分闸式非易失性存储器件的制造方法

    公开(公告)号：US07488649B2

    公开(公告)日：2009-02-10

    申请号：US11645739

    申请日：2006-12-27

    申请人： Yong Jun Lee

    发明人： Yong Jun Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： A method of manufacturing a split gate type non-volatile memory device includes the steps of defining an active region on a semiconductor substrate; forming a pair of first conductive film patterns, each having an electric charge storage layer interposed between the substrate and the first conductive film pattern, on the active region; forming a second conductive film on top of the first conductive film patterns and a remainder of the active region; etchbacking the entire surface of the second conductive film to planarize a top of the second conductive film formed between the first conductive film patterns; forming a photoresist pattern, with an opening corresponding to the active region between the first conductive film patterns, on the second conductive film; and forming a pair of split gates each having one of the first conductive film patterns and a second conductive film pattern formed by patterning the second conductive film using the photoresist pattern as an etching mask.

    摘要翻译： 分离栅型非易失性存储器件的制造方法包括以下步骤：在半导体衬底上限定有源区; 形成一对第一导电膜图案，每个第一导电膜图案在活性区域上具有介于基板和第一导电膜图案之间的电荷存储层; 在所述第一导电膜图案的顶部和所述有源区的其余部分上形成第二导电膜; 回蚀所述第二导电膜的整个表面以平坦化形成在所述第一导电膜图案之间的所述第二导电膜的顶部; 在所述第二导电膜上形成具有对应于所述第一导电膜图案之间的有源区的开口的光致抗蚀剂图案; 以及形成一对分离栅极，每个分离栅极具有第一导电膜图案之一和通过使用光致抗蚀剂图案将蚀刻掩模图案化第二导电膜而形成的第二导电膜图案。

    Method of manufacturing non-volatile memory device
    4.
    发明申请
    Method of manufacturing non-volatile memory device 失效
    制造非易失性存储器件的方法

    公开(公告)号：US20070148868A1

    公开(公告)日：2007-06-28

    申请号：US11643880

    申请日：2006-12-22

    申请人： Yong Jun Lee

    发明人： Yong Jun Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28282 ,  H01L29/4234 ,  H01L29/792

    摘要： A method of manufacturing a non-volatile memory device includes the steps of: defining an active region on a semiconductor substrate; forming a charge storage layer on the active region; forming a first conductive pattern on the charge storage layer, wherein the first conductive pattern has a bottom portion larger in width than a top portion thereof, the first conductive pattern further having a sloping sidewall connecting the top and bottom portions; forming an oxide layer on the sidewall of the first conductive pattern; forming a conformal second conductive layer on the first conductive pattern and on the active region around the first conductive pattern; and patterning the first conductive pattern and the second conductive layer to form a pair of first electrodes and a pair of second electrodes, respectively.

    摘要翻译： 制造非易失性存储器件的方法包括以下步骤：在半导体衬底上限定有源区; 在有源区上形成电荷存储层; 在所述电荷存储层上形成第一导电图案，其中所述第一导电图案具有宽度大于其顶部的底部，所述第一导电图案还具有连接所述顶部和底部的倾斜侧壁; 在第一导电图案的侧壁上形成氧化物层; 在所述第一导电图案上以及围绕所述第一导电图案的所述有源区上形成保形第二导电层; 以及图案化所述第一导电图案和所述第二导电层，以分别形成一对第一电极和一对第二电极。

    Method for fabricating semiconductor device
    7.
    发明授权
    Method for fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07563667B2

    公开(公告)日：2009-07-21

    申请号：US12002241

    申请日：2007-12-13

    申请人： Choul Joo Ko ,  Yong Jun Lee

    发明人： Choul Joo Ko ,  Yong Jun Lee

    IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L21/8242 ,  H01L21/336

    CPC分类号： H01L27/0629 ,  H01L28/40

    摘要： In a method for forming a semiconductor device, a device isolation layer is formed in a capacitor region of a silicon substrate, and a bottom electrode and a dielectric layer are formed on the device isolation layer. Insulation sidewalls are formed on both sides of the bottom electrode. A top electrode is formed on the dielectric layer, and simultaneously a gate electrode is formed in a transistor region of the silicon substrate. Source/drain impurity regions are formed in the silicon substrate at both sides of the gate electrode.

    摘要翻译： 在形成半导体器件的方法中，在硅衬底的电容器区域中形成器件隔离层，并且在器件隔离层上形成底电极和电介质层。 绝缘侧壁形成在底部电极的两侧。 在电介质层上形成顶部电极，同时在硅衬底的晶体管区域形成栅电极。 源极/漏极杂质区域形成在栅极电极两侧的硅衬底中。

    Method for fabricating semiconductor device
    8.
    发明申请
    Method for fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20080176370A1

    公开(公告)日：2008-07-24

    申请号：US12002241

    申请日：2007-12-13

    申请人： Choul Joo Ko ,  Yong Jun Lee

    发明人： Choul Joo Ko ,  Yong Jun Lee

    IPC分类号： H01L21/76

    CPC分类号： H01L27/0629 ,  H01L28/40

    摘要： In a method for forming a semiconductor device, a device isolation layer is formed in a capacitor region of a silicon substrate, and a bottom electrode and a dielectric layer are formed on the device isolation layer. Insulation sidewalls are formed on both sides of the bottom electrode. A top electrode is formed on the dielectric layer, and simultaneously a gate electrode is formed in a transistor region of the silicon substrate. Source/drain impurity regions are formed in the silicon substrate at both sides of the gate electrode.

    摘要翻译： 在形成半导体器件的方法中，在硅衬底的电容器区域中形成器件隔离层，在器件隔离层上形成底部电极和电介质层。 绝缘侧壁形成在底部电极的两侧。 在电介质层上形成顶部电极，同时在硅衬底的晶体管区域中形成栅电极。 源极/漏极杂质区域形成在栅极电极两侧的硅衬底中。

    Hydraulic actuator to which limit-adjustable mechanical lock device is applied
    9.
    发明授权
    Hydraulic actuator to which limit-adjustable mechanical lock device is applied 有权

    公开(公告)号：US10480548B2

    公开(公告)日：2019-11-19

    申请号：US15539400

    申请日：2016-09-30

    申请人： Yong Jun Lee

    发明人： Yong Jun Lee

    IPC分类号： F15B15/24 ,  F15B15/26 ,  F16K31/12 ,  F15B15/14 ,  F15B15/06 ,  F16K31/163 ,  F16H19/04

    摘要： A hydraulic actuator to which a limit-adjustable mechanical lock device is applied, comprising: a housing having a first hole; side covers coupled at both sides of the housing, and having holder insertion holes formed to be opened toward the first hole side of the housing, and plugs; a first holder of which one side of the outer peripheral surface is inserted into the holder insertion hole at the plug side of the side cover by screw coupling; a second holder fitted and coupled to the inner peripheral surface of the side cover and having one end thereof screw-coupled to the second hole of the first holder; a locking means into which a rod is inserted so as to be movable in an axial direction at a predetermined distance across the second hole of the first holder and the third hole of the second holder.