-
公开(公告)号：US20080280447A1
公开(公告)日：2008-11-13
申请号：US11746217
申请日：2007-05-09
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/76808
摘要： A system and method of preventing pattern lifting during a trench etch/clean process is disclosed. A first layer comprising a first dip is formed over a first via pattern. A trench resist layer is formed. The trench resist layer is patterned with a trench reticle to produce a second via pattern in the trench resist layer over the first via pattern. A photo resist over the first via pattern is opened during a trench processing. Thus, an additional pattern added on a trench pattern reticle is used to open, i.e., remove resist over, a huge via feature area causing under layer dip.
摘要翻译： 公开了一种在沟槽蚀刻/清洁过程中防止图案提升的系统和方法。 在第一通孔图案上形成包括第一浸渍的第一层。 形成沟槽抗蚀剂层。 用沟槽掩模版图案化沟槽抗蚀剂层，以在第一通孔图案上的沟槽抗蚀剂层中产生第二通孔图案。 在沟槽处理期间打开第一通孔图案上的光刻胶。 因此，使用添加在沟槽图案掩模版上的附加图案来打开，即，去除导致下层浸渍的巨大通孔特征区域的抗蚀剂。
-
公开(公告)号：US20090050604A1
公开(公告)日：2009-02-26
申请号：US11843361
申请日：2007-08-22
IPC分类号： G03F1/00
CPC分类号： H01L21/31144 , H01L21/02079 , H01L21/0271
摘要： Exemplary embodiments provide a tri-layer resist (TLR) stack used in a photolithographic process, and methods for resist reworking by a single plasma etch process. The single plasma etch process can be used to remove one or more portions/layers of the TLR stack that needs to be reworked in a single process. The removed portions/layers can then be re-formed and resulting in a reworked TLR stack for subsequent photo-resist (PR) processing. The disclosed plasma-etch resist rework method can be a fast, simple, and cost effective process used in either single or dual damascene tri-layer patterning processes for the fabrication of, for example, sub 45-nm node semiconductor structures.
摘要翻译： 示例性实施例提供了在光刻工艺中使用的三层抗蚀剂（TLR）堆叠，以及通过单个等离子体蚀刻工艺来抵抗再加工的方法。 单个等离子体蚀刻工艺可用于去除在单个工艺中需要重新加工的TLR堆叠的一个或多个部分/层。 然后可以重新形成去除的部分/层，并导致用于随后的光致抗蚀剂（PR）处理的返工TLR堆叠。 所公开的等离子体蚀刻抗蚀剂返修方法可以是用于制造例如子45nm节点半导体结构的单镶嵌或双镶嵌三层图案化工艺中的快速，简单和成本有效的工艺。
-
公开(公告)号：US07811942B2
公开(公告)日：2010-10-12
申请号：US11843361
申请日：2007-08-22
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31144 , H01L21/02079 , H01L21/0271
摘要： Exemplary embodiments provide a tri-layer resist (TLR) stack used in a photolithographic process, and methods for resist reworking by a single plasma etch process. The single plasma etch process can be used to remove one or more portions/layers of the TLR stack that needs to be reworked in a single process. The removed portions/layers can then be re-formed and resulting in a reworked TLR stack for subsequent photo-resist (PR) processing. The disclosed plasma-etch resist rework method can be a fast, simple, and cost effective process used in either single or dual damascene tri-layer patterning processes for the fabrication of, for example, sub 45-nm node semiconductor structures.
摘要翻译： 示例性实施例提供了在光刻工艺中使用的三层抗蚀剂（TLR）堆叠，以及通过单个等离子体蚀刻工艺来抵抗再加工的方法。 单个等离子体蚀刻工艺可用于去除在单个工艺中需要重新加工的TLR堆叠的一个或多个部分/层。 然后可以重新形成去除的部分/层，并导致用于随后的光致抗蚀剂（PR）处理的返工TLR堆叠。 所公开的等离子体蚀刻抗蚀剂返修方法可以是用于制造例如子45nm节点半导体结构的单镶嵌或双镶嵌三层图案化工艺中的快速，简单和成本有效的工艺。
-
公开(公告)号：US07569486B2
公开(公告)日：2009-08-04
申请号：US11746217
申请日：2007-05-09
IPC分类号： H01L21/311 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/31144 , H01L21/76808
摘要： A system and method of preventing pattern lifting during a trench etch/clean process is disclosed. A first layer comprising a first dip is formed over a first via pattern. A trench resist layer is formed. The trench resist layer is patterned with a trench reticle to produce a second via pattern in the trench resist layer over the first via pattern. A photo resist over the first via pattern is opened during a trench processing. Thus, an additional pattern added on a trench pattern reticle is used to open, i.e., remove resist over, a huge via feature area causing under layer dip.
摘要翻译： 公开了一种在沟槽蚀刻/清洁过程中防止图案提升的系统和方法。 在第一通孔图案上形成包括第一浸渍的第一层。 形成沟槽抗蚀剂层。 用沟槽掩模版图案化沟槽抗蚀剂层，以在第一通孔图案上的沟槽抗蚀剂层中产生第二通孔图案。 在沟槽处理期间打开第一通孔图案上的光刻胶。 因此，使用添加在沟槽图案掩模版上的附加图案来打开，即，去除导致下层浸渍的巨大通孔特征区域的抗蚀剂。
-
公开(公告)号：US20090170221A1
公开(公告)日：2009-07-02
申请号：US11965972
申请日：2007-12-28
IPC分类号： H01L21/66
CPC分类号： H01L21/76808 , H01L21/02063 , H01L21/76814
摘要： Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a second overash operation. The ashing operation is performed prior to etching of an etch stop layer. The operation removes residue from a cavity formed during formation of the interconnect structure and facilitates better CD control without altering the cavity profiles.
摘要翻译： 提供了形成双镶嵌互连结构的方法。 该方法包括灰化操作，其包括第一灰分操作和第二溢出操作。 灰蚀操作在刻蚀停止层之前进行。 该操作从在形成互连结构期间形成的空腔中去除残留物，并且便于更好的CD控制而不改变空腔轮廓。
-
公开(公告)号：US07910477B2
公开(公告)日：2011-03-22
申请号：US11965972
申请日：2007-12-28
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/02063 , H01L21/76814
摘要： Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a second overash operation. The ashing operation is performed prior to etching of an etch stop layer. The operation removes residue from a cavity formed during formation of the interconnect structure and facilitates better CD control without altering the cavity profiles.
摘要翻译： 提供了形成双镶嵌互连结构的方法。 该方法包括灰化操作，其包括第一灰分操作和第二溢出操作。 灰蚀操作在刻蚀停止层之前进行。 该操作从在形成互连结构期间形成的空腔中去除残留物，并且便于更好的CD控制而不改变空腔轮廓。
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.017 秒)
