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公开(公告)号：US07811942B2
公开(公告)日：2010-10-12
申请号：US11843361
申请日：2007-08-22
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31144 , H01L21/02079 , H01L21/0271
摘要： Exemplary embodiments provide a tri-layer resist (TLR) stack used in a photolithographic process, and methods for resist reworking by a single plasma etch process. The single plasma etch process can be used to remove one or more portions/layers of the TLR stack that needs to be reworked in a single process. The removed portions/layers can then be re-formed and resulting in a reworked TLR stack for subsequent photo-resist (PR) processing. The disclosed plasma-etch resist rework method can be a fast, simple, and cost effective process used in either single or dual damascene tri-layer patterning processes for the fabrication of, for example, sub 45-nm node semiconductor structures.
摘要翻译： 示例性实施例提供了在光刻工艺中使用的三层抗蚀剂（TLR）堆叠，以及通过单个等离子体蚀刻工艺来抵抗再加工的方法。 单个等离子体蚀刻工艺可用于去除在单个工艺中需要重新加工的TLR堆叠的一个或多个部分/层。 然后可以重新形成去除的部分/层，并导致用于随后的光致抗蚀剂（PR）处理的返工TLR堆叠。 所公开的等离子体蚀刻抗蚀剂返修方法可以是用于制造例如子45nm节点半导体结构的单镶嵌或双镶嵌三层图案化工艺中的快速，简单和成本有效的工艺。
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公开(公告)号：US07569486B2
公开(公告)日：2009-08-04
申请号：US11746217
申请日：2007-05-09
IPC分类号： H01L21/311 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/31144 , H01L21/76808
摘要： A system and method of preventing pattern lifting during a trench etch/clean process is disclosed. A first layer comprising a first dip is formed over a first via pattern. A trench resist layer is formed. The trench resist layer is patterned with a trench reticle to produce a second via pattern in the trench resist layer over the first via pattern. A photo resist over the first via pattern is opened during a trench processing. Thus, an additional pattern added on a trench pattern reticle is used to open, i.e., remove resist over, a huge via feature area causing under layer dip.
摘要翻译： 公开了一种在沟槽蚀刻/清洁过程中防止图案提升的系统和方法。 在第一通孔图案上形成包括第一浸渍的第一层。 形成沟槽抗蚀剂层。 用沟槽掩模版图案化沟槽抗蚀剂层，以在第一通孔图案上的沟槽抗蚀剂层中产生第二通孔图案。 在沟槽处理期间打开第一通孔图案上的光刻胶。 因此，使用添加在沟槽图案掩模版上的附加图案来打开，即，去除导致下层浸渍的巨大通孔特征区域的抗蚀剂。
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公开(公告)号：US20080280447A1
公开(公告)日：2008-11-13
申请号：US11746217
申请日：2007-05-09
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/76808
摘要： A system and method of preventing pattern lifting during a trench etch/clean process is disclosed. A first layer comprising a first dip is formed over a first via pattern. A trench resist layer is formed. The trench resist layer is patterned with a trench reticle to produce a second via pattern in the trench resist layer over the first via pattern. A photo resist over the first via pattern is opened during a trench processing. Thus, an additional pattern added on a trench pattern reticle is used to open, i.e., remove resist over, a huge via feature area causing under layer dip.
摘要翻译： 公开了一种在沟槽蚀刻/清洁过程中防止图案提升的系统和方法。 在第一通孔图案上形成包括第一浸渍的第一层。 形成沟槽抗蚀剂层。 用沟槽掩模版图案化沟槽抗蚀剂层，以在第一通孔图案上的沟槽抗蚀剂层中产生第二通孔图案。 在沟槽处理期间打开第一通孔图案上的光刻胶。 因此，使用添加在沟槽图案掩模版上的附加图案来打开，即，去除导致下层浸渍的巨大通孔特征区域的抗蚀剂。
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公开(公告)号：US20090050604A1
公开(公告)日：2009-02-26
申请号：US11843361
申请日：2007-08-22
IPC分类号： G03F1/00
CPC分类号： H01L21/31144 , H01L21/02079 , H01L21/0271
摘要： Exemplary embodiments provide a tri-layer resist (TLR) stack used in a photolithographic process, and methods for resist reworking by a single plasma etch process. The single plasma etch process can be used to remove one or more portions/layers of the TLR stack that needs to be reworked in a single process. The removed portions/layers can then be re-formed and resulting in a reworked TLR stack for subsequent photo-resist (PR) processing. The disclosed plasma-etch resist rework method can be a fast, simple, and cost effective process used in either single or dual damascene tri-layer patterning processes for the fabrication of, for example, sub 45-nm node semiconductor structures.
摘要翻译： 示例性实施例提供了在光刻工艺中使用的三层抗蚀剂（TLR）堆叠，以及通过单个等离子体蚀刻工艺来抵抗再加工的方法。 单个等离子体蚀刻工艺可用于去除在单个工艺中需要重新加工的TLR堆叠的一个或多个部分/层。 然后可以重新形成去除的部分/层，并导致用于随后的光致抗蚀剂（PR）处理的返工TLR堆叠。 所公开的等离子体蚀刻抗蚀剂返修方法可以是用于制造例如子45nm节点半导体结构的单镶嵌或双镶嵌三层图案化工艺中的快速，简单和成本有效的工艺。
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5.发明授权公开(公告)号：US08569838B2
公开(公告)日：2013-10-29
申请号：US13049862
申请日：2011-03-16
IPC分类号： H01L21/70
CPC分类号： H01L29/66484 , H01L21/28123 , H01L21/823828 , H01L27/0207 , H01L29/78
摘要： A method of fabricating gate level electrodes and interconnects in an integrated circuit, and an integrated circuit so fabricated, with improved process margin for the gate level interconnects of a width near the critical dimension. Off-axis illumination, as used in the photolithography of deep sub-micron critical dimension, is facilitated by the patterned features having a preferred orientation in a common direction, with a pitch constrained to within a relatively narrow range. Interconnects in that same gate level, for example “field poly” interconnects, that run parallel to an array of gate elements are placed within a specified distance range from the ends of the gate elements, or at a distance sufficient to allow sub-resolution assist features.
摘要翻译： 一种在集成电路中制造栅极电极和互连的方法，以及如此制造的集成电路，其具有改进的临界尺寸附近的栅极级互连的工艺裕度。 在深亚微米临界尺寸的光刻中使用的离轴照明通过具有在相同方向上具有优选取向的图案化特征促进，其间距限制在相对较窄的范围内。 在与栅极元件阵列平行的同一栅极级别（例如，“多晶”互连）的互连被放置在从栅极元件的端部指定的距离范围内，或者距离足以允许次级分辨率辅助 特征。
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公开(公告)号：US08147633B2
公开(公告)日：2012-04-03
申请号：US13175813
申请日：2011-07-01
申请人： Soo Hyun Lyoo , Yong Seok Choi
发明人： Soo Hyun Lyoo , Yong Seok Choi
CPC分类号： B32B18/00 , C04B2235/36 , C04B2235/5436 , C04B2235/5445 , C04B2235/656 , C04B2237/343 , C04B2237/56 , C04B2237/588 , C04B2237/62 , C04B2237/68 , C04B2237/702 , C04B2237/704 , H01G4/129 , H01G4/30 , H05K3/4629 , H05K3/4688 , H05K2201/0209 , H05K2201/0266 , Y10T428/24926 , Y10T428/2495 , Y10T428/252
摘要： There are provided a method of manufacturing a ceramic sintered body. A method of manufacturing a ceramic sintered body according to one aspect of the invention may include: preparing at least one ceramic sheet having first ceramic particles and glass particles; preparing at least one constraining sheet having second ceramic particles having a smaller particle size than the glass particles and the first ceramic particles; forming a ceramic laminate by alternating the ceramic sheet and the constraining sheet while the ceramic sheet and the constraining sheet are in contact with each other; and sintering the ceramic laminate so that components, which do not react with the first ceramic particles, from the glass particle are moved into the constraining sheet to sinter the constraining sheet when the ceramic sheet is sintered.
摘要翻译： 提供了制造陶瓷烧结体的方法。 根据本发明的一个方面的陶瓷烧结体的制造方法可以包括：制备至少一个具有第一陶瓷颗粒和玻璃颗粒的陶瓷片; 制备具有比玻璃颗粒和第一陶瓷颗粒小的粒径的第二陶瓷颗粒的至少一个约束片; 通过在陶瓷片和约束片彼此接触的同时交替陶瓷片和约束片形成陶瓷层压体; 并且烧结陶瓷层压体，使得当陶瓷片烧结时，不与第一陶瓷颗粒反应的组分从玻璃颗粒移动到约束片中以烧结约束片。
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公开(公告)号：US20110277912A1
公开(公告)日：2011-11-17
申请号：US13175813
申请日：2011-07-01
申请人： Soo Hyun Lyoo , Yong Seok Choi
发明人： Soo Hyun Lyoo , Yong Seok Choi
IPC分类号： C04B37/00
CPC分类号： B32B18/00 , C04B2235/36 , C04B2235/5436 , C04B2235/5445 , C04B2235/656 , C04B2237/343 , C04B2237/56 , C04B2237/588 , C04B2237/62 , C04B2237/68 , C04B2237/702 , C04B2237/704 , H01G4/129 , H01G4/30 , H05K3/4629 , H05K3/4688 , H05K2201/0209 , H05K2201/0266 , Y10T428/24926 , Y10T428/2495 , Y10T428/252
摘要： There are provided a method of manufacturing a ceramic sintered body. A method of manufacturing a ceramic sintered body according to one aspect of the invention may include: preparing at least one ceramic sheet having first ceramic particles and glass particles; preparing at least one constraining sheet having second ceramic particles having a smaller particle size than the glass particles and the first ceramic particles; forming a ceramic laminate by alternating the ceramic sheet and the constraining sheet while the ceramic sheet and the constraining sheet are in contact with each other; and sintering the ceramic laminate so that components, which do not react with the first ceramic particles, from the glass particle are moved into the constraining sheet to sinter the constraining sheet when the ceramic sheet is sintered.
摘要翻译： 提供了制造陶瓷烧结体的方法。 根据本发明的一个方面的陶瓷烧结体的制造方法可以包括：制备至少一个具有第一陶瓷颗粒和玻璃颗粒的陶瓷片; 制备具有比玻璃颗粒和第一陶瓷颗粒小的粒径的第二陶瓷颗粒的至少一个约束片; 通过在陶瓷片和约束片彼此接触的同时交替陶瓷片和约束片形成陶瓷层压体; 并且烧结陶瓷层压体，使得当陶瓷片烧结时，不与第一陶瓷颗粒反应的组分从玻璃颗粒移动到约束片中以烧结约束片。
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公开(公告)号：US20110064952A1
公开(公告)日：2011-03-17
申请号：US12650801
申请日：2009-12-31
申请人： Min Ji Ko , Yong Seok Choi
发明人： Min Ji Ko , Yong Seok Choi
CPC分类号： B32B18/00 , C04B2235/9615 , C04B2237/32 , C04B2237/66 , Y10T428/31504
摘要： A method of fabricating a ceramic substrate includes: preparing a firing theta; forming a ceramic laminated body comprising at least one internal confinement layer on the ceramic theta; providing a temperature-compensation ceramic layer on at least one of a top surface of the ceramic laminated body and a bottom surface of the ceramic laminated body contacting the firing theta, the temperature-compensation ceramic layer having a different initial firing shrinkage temperature than the ceramic laminated body; and firing the ceramic laminated body.
摘要翻译： 制造陶瓷基板的方法包括：制备烧制θ; 形成陶瓷层压体，其包括在陶瓷θ上的至少一个内部限制层; 在陶瓷层叠体的上表面和陶瓷层叠体的与烧成点θ接触的底面中的至少一个上提供温度补偿陶瓷层，所述温度补偿陶瓷层的初始烧制收缩温度与陶瓷不同 层压体 并烧制陶瓷层压体。
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9.发明申请METHOD OF MANUFACTURING CAPACITOR-EMBEDDED LOW TEMPERATURE CO-FIRED CERAMIC SUBSTRATE 审中-公开制造电容器嵌入式低温合成陶瓷基板的方法公开(公告)号：US20100170708A1
公开(公告)日：2010-07-08
申请号：US12724239
申请日：2010-03-15
申请人： Seung Gyo Jeong , Yong Seok Choi , Ki Pyo Hong
发明人： Seung Gyo Jeong , Yong Seok Choi , Ki Pyo Hong
IPC分类号： H05K1/18
CPC分类号： H01G4/30 , H01G4/232 , H01L2224/48091 , H01L2924/01019 , H01L2924/09701 , H01L2924/30107 , H05K1/0231 , H05K1/0306 , H05K1/162 , H05K1/186 , H05K3/4611 , H05K3/4629 , H05K3/4688 , H05K2201/09672 , H05K2201/10636 , Y02P70/611 , Y10T29/43 , Y10T29/435 , Y10T29/49117 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165 , H01L2924/00014 , H01L2924/00
摘要： A method of manufacturing a capacitor-embedded low temperature co-fired ceramic substrate. A capacitor part is manufactured by firing a deposition including at least one high dielectric ceramic sheet to form a capacitor part. A plurality of low temperature co-fired green sheets are provided. Each of the low temperature co-fired green sheet has at least one of a conductive pattern and a conductive via hole thereon. A low temperature co-fired ceramic deposition is formed by depositing the low temperature co-fired green sheets to embed the capacitor part in the low temperature co-fired ceramic deposition. The embedded capacitor part is connected either to the conductive pattern or the conductive via hole of an adjacent green sheet. Then the low temperature co-fired ceramic deposition having the capacitor part embedded therein is fired.
摘要翻译： 一种制造电容器嵌入式低温共烧陶瓷基板的方法。 通过烧结包括至少一个高介电陶瓷片的沉积来形成电容器部分来制造电容器部分。 提供多个低温共烧生片。 每个低温共烧生片具有导电图案和导电通孔中的至少一个。 通过沉积低温共烧生片将电容器部分嵌入低温共烧陶瓷沉积中形成低温共烧陶瓷沉积。 嵌入式电容器部分连接到相邻生片的导电图案或导电通孔。 然后烧结具有嵌入其中的电容器部分的低温共烧陶瓷沉积。
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公开(公告)号：US20100059165A1
公开(公告)日：2010-03-11
申请号：US12550907
申请日：2009-08-31
申请人： Ho Sung CHOO , Jong Myeon Lee , Yong Seok Choi
发明人： Ho Sung CHOO , Jong Myeon Lee , Yong Seok Choi
IPC分类号： B32B37/14
CPC分类号： B32B37/0023 , B32B2305/77 , B32B2315/02 , H05K1/0306 , H05K1/183 , H05K3/4629 , H05K3/4697 , H05K2201/0166 , H05K2203/063 , H05K2203/308
摘要： A method of manufacturing a multilayer ceramic substrate having a cavity includes preparing a first ceramic laminate having an opening for forming a cavity, and a second ceramic laminate which is to be provided on a bottom surface of the first ceramic laminate, forming a polymer layer in a region corresponding at least to the opening, on a top surface of the second ceramic laminate, forming a desired multilayer ceramic laminate by laminating the first and second ceramic laminates such that the polymer layer of the second ceramic laminate is placed under the opening, laminating first and second constraining layers on a top surface and a bottom surface of the multilayer ceramic laminate, respectively, and sintering the multilayer ceramic laminate including the laminated first and second constraining layers. Accordingly, the strength of a low temperature co-fired ceramic (LTCC) substrate having a cavity is enhanced, and an effective area for mounting built-in devices can be increased.
摘要翻译： 制造具有空腔的多层陶瓷基板的方法包括制备具有用于形成空腔的开口的第一陶瓷层压体和将设置在第一陶瓷层压板的底表面上的第二陶瓷层压体，形成聚合物层 至少对应于所述开口的区域，在所述第二陶瓷层叠体的顶表面上，通过层压所述第一和第二陶瓷层压体形成期望的多层陶瓷层压体，使得所述第二陶瓷层压体的聚合物层位于所述开口下方，层压 第一和第二限制层分别在多层陶瓷层压板的顶表面和底表面上，并且烧结包括层叠的第一和第二约束层的多层陶瓷层压体。 因此，提高了具有空腔的低温共烧陶瓷（LTCC）基板的强度，能够提高安装内置装置的有效面积。
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